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| part number 440gr revision 1.19 ? may 07, 2008 amcc proprietary 1 440gr powerpc 440gr embedded processor preliminary data sheet features ?powerpc ? 440 processor core operating up to 667mhz with 32kb i-cache and d-cache with parity checking. ? selectable processor:bus cl ock ratios of n:1, n:2. ? dual bridged processor local buses (plbs) with 64- and 128-bit widths. ? double data rate (ddr) synchronous dram (sdram) interface operating up to 133mhz with ecc. ? dma support for external peripherals, internal uart and memory. ? pci v2.2 interface (3.3v on ly). thirty-two bits at up to 66mhz. ? programmable interrupt controller supports interrupts from a variety of sources. ? programmable general purpose timers (gpt). ? two ethernet 10/100mbps half- or full-duplex interfaces. operational modes supported are mii, rmii, and smii with packet reject. ? up to four serial ports (16550 compatible uart). ? external peripheral bus (16-bit data) for up to six devices with external mastering. ? two iic interfaces (one with boot parameter read capability). ? nand flash interface. ? spi interface. ? general purpose i/o (gpio) interface. ? jtag interface for board level testing. ? boot from pci memory, nor flash on the external peripheral bus, or nand flash on the nand flash interface. ? available in rohs compliant lead-free package. description designed specifically to address high-end embedded applications, the powe rpc 440gr (ppc440gr) provides a high-performance, low- power solution that interfaces to a wide range of peripherals and incorporates on-chip power management features. this chip contains a high-performance risc processor, ddr sdram contro ller, pci bus interface, control for external rom and peripherals, dma with scatter-gather support, ethernet ports, serial ports, iic interfaces, spi interface, nand flash interface, and general purpose i/o. technology: cmos cu-11, 0.13 m. package: 35mm, 456-ball enhanced plastic ball grid array (e-pbga). typical power (estimated): less than 2.5w at 533mhz, 2.3w at 400mhz. supply voltages required: 3.3v, 2.5v, 1.5v.
2 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor contents ordering and pvr information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 address maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 powerpc 440 processor core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 internal buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ddr sdram memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 external peripheral bus controller (ebc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ethernet controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 dma to plb3 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 serial ports (uart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 serial ports (uart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 iic bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 serial peripheral interface (spi/scp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 nand flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 general purpose timers (gpt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 general purpose io (gpio) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 universal interrupt controller (uic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 signal lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 spread spectrum clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ddr sdram i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ddr sdram write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 ddr sdram read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 amcc proprietary 3 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 figures figure 1. order part number key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. ppc440gr functional block diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. 35mm, 456-ball e-pbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 4. overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 5. timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 6. input setup and hold waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 7. output delay and float timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 8. ddr sdram simulation signal termin ation model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 9. ddr sdram write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 10. ddr sdram memclkout0 and read clock delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 11. ddr sdram read data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 12. ddr sdram read cycle timing?example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 13. ddr sdram read cycle timing?example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 14. ddr sdram read cycle timing?example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 tables table 1. system memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. dcr address map (4kb of device configuration registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. recommended reflow soldering profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. jedec moisture sensitivity level and ball composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. signals listed alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. signals listed by ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 7. pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 8. non-functional ball connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 9. signal functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 10. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 11. recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 12. overshoot and undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 13. input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 14. typical dc power supply requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 15. v dd supply power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 16. dc power supply loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 17. package thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 18. clocking specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 19. peripheral interface clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 20. i/o specifications?pci, uart, iic, spi, ethernet, system and debug interfaces . . . . . . . . . . . . . . 73 table 21. i/o specifications?ebc, ebmi, dma and nand flash interf aces . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 22. ddr sdram output driver specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 23. i/o timing?ddr sdram t ds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 24. i/o timing?ddr sdram t sk , t sa , and t ha . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor table 25. i/o timing?ddr sdram t sd and t hd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 26. i/o timing?ddr sdram t sin and t din . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 27. strapping pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 amcc proprietary 5 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 ordering and pvr information for information on the availabilit y of the following parts, contac t your local am cc sales office. each part number contains a revision code. this is the die mask revision number and is included in the part number for identification purposes only. the pvr (processor version register) and the jtag id register ar e software accessible (read-only). refer to the ppc440gr user?s manual for details on accessing these registers. figure 1. order part number key product name order part number (see notes: ) package revision level pvr value jtag id ppc440gr ppc440gr-3pbfffcx 35mm, 456 ball, e-pbga b 0x422218d4 0x2a950049 notes: 1. p = module package type b = e-pbga and contains lead. j = e-pbga and is lead-free (rohs compliant). 2. b = chip revision level b = revision level b (1.1) 3. fff = processor frequency 333 = 333mhz 400 = 400mhz 533 = 533mhz 667 = 667mhz 4. c = case temperature range: -40c to +90c for 333mhz and 400mhz parts -40c to +100c for 533mhz parts -40c to 90c for 333mhz and 400mhz parts -40c to +85c for 667mhz parts 5. x = shipping package type z = tape-and-reel blank = tray amcc part number ppc440gr-3jb667cz package processor frequency grade 3 reliability case temperature range revision level shipping package note: the example p/n above is lead-free, capabl e of running at 667 mhz, and is shipped in tape-and-reel packaging. 6 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor block diagram figure 2. ppc440gr functional block diagram the ppc440gr is a system on a chip (soc) using ibm coreconnect bus ? architecture. processor core dcr bus 32kb on-chip peripheral bus (opb) gpio iic uart dma bridge plb4 (128 bits) ddr sdram external peripheral controller controller clock control reset power mgmt jtag trace timers mmu controller opb - 30-bit addr - 16-bit data - 13-bit addr - 32-bit data nand flash controller i-cache 32kb d-cache ppc440 pci bridge x2 x4 mal ethernet x2 dcrs gpt 1 mii or 2 rmii or 2 smii zmii 66mhz max 10/100 66mhz max 266mhz data rate plb3 (64 bits) plb bridge spi - 32 bits - 6 devices performance monitor bsc dma controller uic external 10 interrupts amcc proprietary 7 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 address maps the ppc440gr incorporates two address maps. the first is a fixed processor system memory address map. this address map defines the possible contents of various address regions which the processor can access. the second is the dcr address map for devi ce configuration registers (dcrs). the dcrs are accessed by software running on the ppc440gr processor through the use of mtdcr and mfdcr instructions. table 1. system memory address map (sheet 1 of 2) function sub function start address end address size local memory 1 ddr sdram 0 0000 0000 0 3fff ffff 1gb reserved 0 4000 0000 0 7fff ffff ebc ebc 0 8000 0000 0 9fff ffff 512mb pci pci memory 0 a000 0000 0 dfff ffff 1gb reserved 0 e000 0000 0 e7ff ffff pci i/o 0 e800 0000 0 e800 ffff 64kb reserved 0 e801 0000 0 e87f ffff pci i/o 0 e880 0000 0 ebff ffff 56mb reserved 0 ec00 0000 0 eebf ffff configuration registers 0 eec0 0000 0 eec0 0007 8b reserved 0 eec0 0008 0 eecf ffff pci interrupt ack / special cycle 0 eed0 0000 0 eed0 0003 4b reserved 0 eed0 0004 0 ef3f ffff local configuration registers 0 ef40 0000 0 ef40 003f 64b reserved 0 ef40 0040 0 ef4f ffff 8 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor internal peripherals reserved 0 ef50 0000 0 ef5f ffff general purpose timer 0 ef60 0000 0 ef60 00ff 256b reserved 0 ef60 0100 0 ef60 02ff uart0 0 ef60 0300 0 ef60 0307 8b reserved 0 ef60 0308 0 ef60 03ff uart1 0 ef60 0400 0 ef60 0407 8b reserved 0 ef60 0408 0 ef60 04ff uart2 0 ef60 0500 0 ef60 0507 8b reserved 0 ef60 0508 0 ef60 05ff uart3 0 ef60 0600 0 ef60 0607 8b reserved 0 ef60 0608 0 ef60 06ff iic0 0 ef60 0700 0 ef60 071f 32b reserved 0 ef60 0720 0 ef60 07ff iic1 0 ef60 0800 0 ef60 081f 32b reserved 0 ef60 0820 0 ef60 08ff spi 0 ef60 0900 0 ef60 0906 6b reserved 0 ef60 0907 0 ef60 09ff opb arbiter 0 ef60 0a00 0 ef60 0a3f 64b reserved 0 ef60 0a40 0 ef60 0aff gpio0 controller 0 ef60 0b00 0 ef60 0b7f 128b reserved 0 ef60 0b80 0 ef60 0bff gpio1 controller 0 ef60 0c00 0 ef60 0c7f 128b reserved 0 ef60 0c80 0 ef60 0cff ethernet phy zmii 0 ef60 0d00 0 ef60 0d0f 16b reserved 0 ef60 0d10 0 ef60 0dff ethernet 0 controller 0 ef60 0e00 0 ef60 0eff 256b ethernet 1 controller 0 ef60 0f00 0 ef60 0fff 256b reserved 0 ef60 1000 0 efff ffff ebc 0 f000 0000 0 ffdf ffff 254mb boot space (ebc bank 0 and pci) 0 ffe0 0000 0 ffff ffff 2mb notes: 1. ddr sdram can be located anywhere in the local memory area of the memory map. 2. ebc and pci are relocatable, but this map reflects the suggested configuration. table 1. system memory address map (sheet 2 of 2) function sub function start address end address size amcc proprietary 9 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 table 2. dcr address map (4kb of device configuration registers) function start address end address size total dcr address space 1 000 3ff 1kw (4kb) 1 by function: reserved 000 00b 12w clocking power on reset 00c 00d 2w system dcrs 00e 00f 2w memory controller 010 011 2w external bus controller 012 013 2w reserved 014 015 2w plb 128 performance monitor 016 017 2w reserved 018 01f 8w plb 128 to plb 64 bridge out 020 02f 16w plb 64 to plb 128 bridge in 030 03f 16w reserved 040 06f 64w plb 64 arbiter 070 08f 16w plb 128 arbiter 080 08f 16w plb 64 to opb bridge out 090 09f 16w reserved 0a0 0a7 8w opb to plb 64 bridge in 0a8 0af 8w power management 0b0 0b7 8w reserved 0b8 0bf 8w interrupt controller 0 0c0 0cf 16w interrupt controller 1 0d0 0df 16w clock, control, and reset 0e0 0ef 16w reserved 0f0 0ff 16w dma to plb 64 controller 100 13f 64w reserved 140 17f 64w ethernet mal 180 1ff 128w reserved 200 2ff 512w dma to plb 128 controller 300 33f 64w reserved 340 3ff 512w notes: 1. dcr address space is addressable with up to 10 bits (1024 or 1k unique addresses). each unique address represents a single 32 -bit (word) register. one kiloword (1024w) equals 4kb (4096 b). 10 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor powerpc 440 processor core the powerpc 440 processor core is designed for high-end applications: raid controlle rs, san, iscsi, routers, switches, printers, set- top boxes, etc. it implements the book e po werpc embedded architecture and uses the 128-bit version of ibm?s on-chip coreconnect bus architecture. features include: ? up to 667mhz operation ? powerpc book e architecture ? 32kb i-cache, 32kb d-cache ? utlb word wide parity on data and tag address parity with exception force ? three logical regions in d-cache: locked, transient, normal ? d-cache full line flush capability ? 41-bit virtual address, 36-bit (64gb) physical address ? superscalar, out-of-order execution ? 7-stage pipeline ? 3 execution pipelines ? dynamic branch prediction ? memory management unit ? 64-entry, full associative, unified tlb with optional parity ? separate instruction and data micro-tlbs ? storage attributes for write-through, cache- inhibited, guarded, and big or little endian ? debug facilities ? multiple instruction and data range breakpoints ? data value compare ? single step, branch, and trap events ? non-invasive real-time trace interface ? 24 dsp instructions ? single cycle multiply and multiply-accumulate ? 32 x 32 integer multiply ? 16 x 16 -> 32-bit mac amcc proprietary 11 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 internal buses the powerpc 440gr features four standard on-chip buses: two processor local buses (plbs), one on-chip peripheral bus (opb), and the device control register bus (dcr). the high performance, high bandwidth cores such as the powerpc 440 processor core, the ddr sdram memory controller, and the pci bridge connect to the plbs. the primary opb hosts lower data rate peripheral s. the daisy-chained dcr provides a lower bandwidth path for passing status and control information betw een the processor core and the other on-chip cores. features include: ? plb 128 (plb4) ? 128-bit implementation of the plb architecture ? separate and simultaneous read and write data paths ? 36-bit address ? simultaneous control, address, and data phases ? four levels of pipelining ? byte-enable capa bility supporting unaligned transfers ? 32- and 64-byte burst transfers ? 133mhz, maximum 4.25gb/s (simultaneous read and write) ? processor:bus clock ratios of n:1 and n:2 ? plb 64 (plb3) ? 64-bit implementation of the plb architecture ? 32-bit address ? 133mhz (1:1 ratio with plb 128), maximum 1.1gb/s (no simultaneous read and write) ?opb ? 32-bit data path ? 32-bit address ? 66.66mhz ? dcr ? 32-bit data path ? 10-bit address 12 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor pci interface the pci interface allows connection of pci devices to th e powerpc processor and local memory. this interface is designed to version 2.2 of the pci specif ication and supports 32- bit pci devices. reference specifications: ? powerpc coreconnect bus (plb) specification version 3.1 ? pci specification version 2.2 ? pci bus power management interface specification version 1.1 features include: ?pci 2.2 ? frequency to 66mhz ? 32-bit bus ? pci host bus bridge or an adapter device's pci interface ? internal pci arbitration function, supporting up to six ex ternal devices, that can be disabled for use with an external arbiter ? support for message signaled interrupts ? simple message passing capability ? asynchronous to the plb ? pci power management 1.1 ? pci register set addressable both from on-chip processor and pci device sides ? ability to boot from pci bus memory ? error tracking/status ? supports initiation of transfer to the following address spaces: ? single beat i/o reads and writes ? single beat and burst memory reads and writes ? single beat configuration reads and writes (type 0 and type 1) ? single beat special cycles ddr sdram memory controller the double data rate (ddr) sdram memo ry controller supports industry standa rd discrete devices. up to four 256mb logical banks are supported in limited configuratio ns. global memory timings, ad dress and bank sizes, and memory addressing modes are programmable. features include: ? registered and non-registered industry standard discrete devices ? 32-bit memory interface with optional 8-bit ecc (sec/ded) ? sustainable 1.1gb/s peak bandwidth at 133mhz ? sstl_2 logic ? 1 to 4 chip selects ? cas latencies of 2, 2.5 and 3 supported ? ddr200/266 support ? page mode accesses (up to eight open pages) with configurable paging policy ? programmable address mapping and timing ? hardware and software initiated self-refresh ? power management (self-refresh, suspend, sleep) amcc proprietary 13 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 external peripheral bus controller (ebc) features include: ? up to six rom, eprom, sram, flash memory , and slave peripheral i/o banks supported ? up to 66.66mhz operation ? burst and non-burst devices ? 16-bit byte-addressable data bus ? 30-bit address ? peripheral device pacing with external ?ready? ? latch data on ready, synchronous or asynchronous ? programmable access timing per device ? 256 wait states for non-burst ? 32 burst wait states for first access and up to 8 wait states for subsequent accesses ? programmable cson, csoff relative to address ? programmable oeon, weon, weoff (1 to 4 clock cycles) relative to cs ? programmable address mapping ? external dma slave support ? external master interface ? write posting from external master ? read prefetching on plb for external master reads ? bursting capable from external master ? allows external master access to all non-ebc plb slaves ? external master can control ebc sl aves for own access and control ethernet controller interface ethernet support provided by the ppc440gr interfaces to the physical layer but the phy is not included on the chip: ? one to two 10/100 interfaces running in full- and half-duplex modes ? one full media independent interface (mii) with 4-bit parallel data transfer ? two reduced media independent interfaces (rmii) with 2-bit parallel data transfer ? two serial media independent interfaces (smii) ? packet reject support dma to plb3 controller this dma controller provides a dma interface between the opb and the 64-bit plb. features include: ? supports the following transfers: ? memory-to-memory transfers ? buffered peripheral to memory transfers ? buffered memory to peripheral transfers ? four channels ? scatter/gather capability for pr ogramming multiple dma operations ? 32-byte buffer ? 8-, 16-, 32-bit peripheral support (opb and external) ? 32-bit addressing ? address increment or decrement ? supports internal and external peripherals ? support for memory mapped peripherals ? support for peripherals running on slower frequency buses 14 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor dma to plb4 controller this dma controller provides a dma interface dedicated to the 128-bit plb. features include: ? support for memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers ? scatter/gather capability ? 128-byte buffer with programmable thresholds serial ports (uart) features include: ? up to four ports in th e following combinations: ? one 8-pin ? two 4-pin ? one 4-pin and two 2-pin ? four 2-pin ? selectable internal or external serial clock to allow wide range of baud rates ? register compatibility wit h ns16550 register set ? complete status reporting capability ? fully programmable serial-i nterface characteristics ? supports dma using internal dma function on plb 64 iic bus interface features include: ? two iic interfaces provided ? support for philips? semiconductors i 2 c specification, dated 1995 ? operation at 100khz or 400khz ?8-bit data ? 10- or 7-bit address ? slave transmitter and receiver ? master transmitter and receiver ? multiple bus masters ? two independent 4 x 1 byte data buffers ? twelve memory-mapped, fully prog rammable configuration registers ? one programmable interrupt request signal ? provides full management of all iic bus protocols ? programmable error recovery ? includes an integrated boot-strap controller (bsc ) that is multiplexed with the iic0 interface amcc proprietary 15 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 serial peripheral interface (spi/scp) the serial peripheral interface (also known as the seri al communications port) is a full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other serial devic es. the scp is a master on the serial port supporting a 3-wire interface (recei ve, transmit, and clock), and is a slave on the opb. features include: ? three-wire serial port interface ? full-duplex synchronous operation ? scp bus master ? opb bus slave ? programmable clock rate divider ? clock inversion ? reverse data ? local data loop back for test nand flash controller the nand flash controller provides a simple interface be tween the ebc and up to four separate external nand flash devices. it provides both direct command, address, an d data access to the external device as well as a memory-mapped linear region that generates data access es. nand flash device data appears on the peripheral data bus. features include: ? 1 to 4 banks supported on ebc ? direct interfacing to: ? discrete nand flash de vices (up to 4 devices) ? smartmedia card socket (22-pins) ? device sizes ? 4mb and larger supporte d for read/w rite access ? 4mb to 256mb boot-from-nand flash (siz e supported depends on addressing mode) ? (512 + 16)-b or (2k + 64)-b device page sizes supported ? boot-from-nand: execute a linear sequence of boot code out of the first 4kb of block 0 ? support dma to allow direct, no-processor-int ervention block copy from nand flash to sdram ? ecc provides single-bit error correction and double-bit error detection in each 256b of stored data ? chip selects shared with ebc general purpose timers (gpt) provides a separate time base counter and additional system timers in addition to those defined in the processor core. features include: ? 32-bit time base counter dr iven by the opb bus clock ? seven 32-bit compare timers general purpose io (gpio) controller ? controller functions and gpio registers are programm ed and accessed via memory-mapped opb bus master accesses. ? 64 gpios are multiplexed with other functions. dcrs control whether a particular pin that has gpio capabilities acts as a gpio or is used for ano ther purpose. ? each gpio output is separately programmable to emulate an open drain driver (that is, drives to zero, tri-stated if output bit is 1). 16 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor universal interrupt controller (uic) two universal interrupt controllers (uic) are employed. they provide control, status, and communications necessary between the external and internal source s of interrupts and the on-chip powerpc processor. note: processor specific interrupts (for exampl e, page faults) do not use uic resources. features include: ? 10 external interrupts ? edge triggered or level-sensitive ? positive or negative active ? non-critical or critical interrupt to the on-chip processor core ? programmable interrupt priority ordering ? programmable critical interrupt ve ctor for faster vector processing jtag features include: ? ieee 1149.1 test access port ? ibm riscwatch debugger support ? jtag boundary scan description language (bsdl) amcc proprietary 17 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 package diagram figure 3. 35mm, 45 6-ball e-pbga package a s 1.27 typ 0.75 0.15 solderball x 456 26 af 35.0 0.2 31.75 35.0 b a c 0.20 ? 0.30 ? 0.15 s c ab s s 0.20 c c 2.49 ref 0.6 0.1 pcb substrate mold compound b c d e f g h j k l m aa n p r t u v w y ab ac ad ae thermal balls 135 7 911131517 19 2 4 6 810 12 14 16 18 21 23 25 20 22 24 top view bottom view 0.25 0.35 c c notes: 1. all dimensions are in mm. 2.65 max 2. package is available in both lead-free (rohs compliant) and leaded versions. gold gate release corresponds to a1 ball location 30 typ ppc440gr 1ywwbzzzzz lot number ppc440gr-nprffft part number ? 18 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor assembly recommendations table 3. recommended reflow soldering profile profile feature sn-pb eutectic assembly pb free reflow assembly average ramp-up rate 3c/second max 3c/second max preheat ? temperature min ? temperature max ? time (min to max) 100c 150c 60-120 seconds 150c 180c 60-120 seconds time maintained above: ? temperature ?time 183c 60-150 seconds 230c 30-50 seconds peak temperature 225 +0/-5c 260 +5/-0c time within 5c of actual peak temperature 10-30 seconds 10-20 seconds ramp-down rate 6c/second max 6c/second max time 25c to peak temperature 6 minutes max 8 minutes max table 4. jedec moisture sensit ivity level and ball composition sn-pb eutectic assembly pb free reflow assembly msl level 3 3 solder ball metallurgy 63sn/37pb sn/4ag/05cu amcc proprietary 19 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 signal lists the following table lists all the external signals in alphab etical order and shows the ball (pin) number on which the signal appears. multiplexed signals are shown with the default signal (following reset) not in brackets and alternate signals in brackets. multiplexed signals appear alphabetically multiple times in the list? once for each signal name on the ball. the page number listed gives the page in ?sig nal functional description? on page 53 where the signals in the indicated interface group begin. in cases where sig nals in the same interface gr oup (for example, ethernet) have different names to distinguish variations in the mo de of operation, the names ar e separated by a comma with the primary mode name appearing first. these signals are listed only once, and appear alphabetically by the primary mode name. table 5. signals listed alphabetically (sheet 1 of 24) signal name ball interface group page agnd ae17 power 60 av dd ad17 ba0 af03 ddr sdram 54 ba1 af04 banksel0 r04 ddr sdram 54 banksel1 r02 banksel2 r01 banksel3 n01 [busreq]gpio31 aa23 external master peripheral 57 cas j02 ddr sdram 54 clken af05 ddr sdram 54 dm0 ae05 ddr sdram 54 dm1 ad07 dm2 j01 dm3 l03 dm8 af07 [dmaack0][irq8]gpio47 d18 external slave peripheral 56 [dmaack1][irq4]gpio44 g25 [dmaack2][peraddr06]gpio01 b06 [dmaack3][peraddr03]gpio04 c07 [dmareq0][irq7]gpio46 b24 external slave peripheral 56 dmareq1[irq5][modectrl] ac12 [dmareq2][peraddr07]gpio00 c08 [dmareq3][peraddr04]gpio03 d08 dqs0 ad09 ddr sdram 54 dqs1 ac08 dqs2 k03 dqs3 m04 dqs8 ac06 [drvrinh1]rejectpkt y25 system 59 [drvrinh2]halt c25 20 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor ecc0 p02 ddr sdram 54 ecc1 n02 ecc2 m01 ecc3 m02 ecc4 n03 ecc5 n04 ecc6 l02 ecc7 m03 [emccd, emc1rxerr]gpio25[nfrdybusy ]ac16 ethernet 55 [emccrs, emc0crsdv]gpio22 ad15 [emcdv, emc1crsdv]gpio21[nfren ]af17 emcmdclk ae16 emcmdio ac18 emcrxclk af19 [emcrxd0, emc0rxd0, emc0rxd]gpio12 ad19 [emcrxd1, emc0rxd1, emc1rxd]gpio13 ae20 [emcrxd2, emc1rxd0]gpio14 ad18 [emcrxd3, emc1rxd1]gpio15 ac17 [emcrxerr, emc0 rxerr]gpio20 ad16 emctxclk, emcrefclk ac15 [emctxd0, emc0txd0, emc0txd]gpio16 ad14 [emctxd1, emc0txd1, emc1txd]gpio17 af13 [emctxd2, emc1txd0]gpio18[nfcle] af14 [emctxd3, emc1txd1]gpio19[nfale] ac14 [emctxen, emc0txen, emcsync]gpio24 af20 [emctxerr, emc1txen]gpio23[nfwen ]af18 [eot0/tc0][irq9]gpio48 a19 external slave peripheral 56 [eot1/tc1][irq6]gpio45 h23 [eot2/tc2][peraddr05]gpio02 a05 [eot3/tc3][peraddr02]gpio05 b04 [extack ]gpio30 aa25 external master peripheral 57 [extreq ]gpio27 ad26 external master peripheral 57 extreset b23 external master peripheral 57 table 5. signals listed alphabetically (sheet 2 of 24) signal name ball interface group page amcc proprietary 21 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 gnd a01 power 60 gnd a02 gnd a06 gnd a09 gnd a11 gnd a16 gnd a21 gnd a26 gnd b02 gnd b25 gnd b26 gnd c03 gnd c24 gnd d04 gnd d21 gnd d23 gnd e09 gnd e14 gnd e18 gnd f01 gnd f26 gnd j05 gnd j22 gnd j26 gnd l01 gnd l04 gnd l11 gnd l13 gnd l14 gnd l16 gnd l26 gnd m12 gnd m13 table 5. signals listed alphabetically (sheet 3 of 24) signal name ball interface group page 22 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor gnd m15 power 60 gnd m25 gnd n05 gnd n11 gnd n13 gnd n14 gnd n15 gnd n16 gnd p11 gnd p12 gnd p13 gnd p14 gnd p16 gnd p22 gnd r12 gnd r14 gnd r15 gnd t01 gnd t11 gnd t13 gnd t14 gnd t16 gnd t26 gnd v05 gnd v01 gnd v22 gnd aa01 gnd aa26 gnd ab09 gnd ab13 gnd ab18 gnd ac01 gnd ac04 gnd ac07 gnd ac23 table 5. signals listed alphabetically (sheet 4 of 24) signal name ball interface group page amcc proprietary 23 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 gnd ad03 power 60 gnd ad24 gnd ae01 gnd ae02 gnd ae25 gnd af01 gnd af06 gnd af11 gnd af16 gnd af21 gnd af25 gnd af26 table 5. signals listed alphabetically (sheet 5 of 24) signal name ball interface group page 24 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor gpio00[peraddr07][dmareq2] c08 system 59 gpio01[peraddr06][dmaack2] b06 gpio02[peraddr05][eot2/tc2] a05 gpio03[peraddr04][dmareq3] d08 gpio04[peraddr03][dmaack3] c07 gpio05[peraddr02][eot3/tc3] b04 gpio06[percs1 ][nfce1 ]c06 gpio07[percs2 ][nfce2 ]a04 gpio08[percs3 ][nfce3 ]b07 gpio09[percs4 ]b10 gpio10[percs5 ]a10 gpio11[pererr] e04 gpio12[emcrxd0, emc0rxd0, emc0rxd] ad19 gpio13[emcrxd1, emc0rxd1, emc1rxd] ae20 gpio14[emcrxd2, emc1rxd0] ad18 gpio15[emcrxd3, emc1rxd1] ac17 gpio16[emctxd0, emc0txd0, emc0txd] ad14 gpio17[emctxd1, emc0txd1, emc1txd] af13 gpio18[emctxd2, emc1txd0][nfcle] af14 gpio19[emctxd3, emc1txd1][nfale] ac14 gpio20[emcrxerr, emc0rxerr] ad16 gpio21[emcdv, emc1crsdv][nfren ]af17 gpio22[emccrs, emc0crsdv] ad15 gpio23[emctxerr, emc1txen][nfwen ]af18 gpio24[emctxen, emc0txen, emcsync] af20 gpio25[emccd, emc1rxerr][nfrdybusy ]ac16 gpio26 ac26 gpio27[extreq ]ad26 gpio28 y24 gpio29[holdack] ab25 gpio30[extack ] aa25 gpio31[busreq] aa23 table 5. signals listed alphabetically (sheet 6 of 24) signal name ball interface group page amcc proprietary 25 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 gpio32 w24 system 59 gpio33 ab26 gpio34[uart0_dcd /uart1_cts/ uart2_tx] r25 gpio35[uart0_dsr /uart1_rts/ uart2_rx] u26 gpio36[uart0_cts /uart3_rx] v26 gpio37[uart0_rts/ uart3_tx] r26 gpio38[uart0_dtr /uart1_tx] n24 gpio39[uart0_ri /uart1_rx] p24 gpio40[irq0] d03 gpio41[irq1] g04 gpio42[irq2] f02 gpio43[irq3] g02 gpio44[irq4][dmaack1] g25 gpio45[irq6][eot1/tc1] h23 gpio46[irq7][dmareq0] b24 gpio47[irq8][dmaack0] d18 gpio48[irq9][eot0/tc0] a19 gpio49[trcbs0] ae21 gpio50[trcbs1] ac25 gpio51[trcbs2] aa24 gpio52[trces0] y03 gpio53[trces1] aa04 gpio54[trces2] ab03 gpio55[trces3] ab04 gpio56[trces4] af22 gpio57[trcts0] ac22 gpio58[trcts1] ae24 gpio59[trcts2] ad04 gpio60[trcts3] ad06 gpio61[trcts4] ac09 gpio62[trcts5] ad12 gpio63[trcts6] ae15 halt [drvrinh2] c25 system 59 holdack[gpio29] ab25 external master peripheral 57 holdpri[leaktest] v24 holdreq[rcvrinh] y23 iic0sclk u25 iic0 peripheral 57 iic0sdata t24 table 5. signals listed alphabetically (sheet 7 of 24) signal name ball interface group page 26 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor [iic1sclk]scpclkout u24 iic1 peripheral 57 [iic1sdata]scpdi v25 [irq0]gpio40 d03 interrupts 58 [irq1]gpio41 g04 [irq2]gpio42 f02 [irq3]gpio43 g02 [irq4]gpio44[dmaack1] g25 [irq5][modectrl]dmareq1 ac12 [irq6]gpio45[eot1/tc1] h23 [irq7]gpio46[dmareq0] b24 [irq8]gpio47[dmaack0] d18 [irq9]gpio48[eot0/tc0] a19 [leaktest]holdpri v24 system 59 memaddr00 p01 ddr sdram 54 memaddr01 p04 memaddr02 t02 memaddr03 t04 memaddr04 u01 memaddr05 v02 memaddr06 u04 memaddr07 w03 memaddr08 y02 memaddr09 ab02 memaddr10 r03 memaddr11 ad01 memaddr12 ad02 memclkout0 af12 ddr sdram 54 memclkout0 ae13 table 5. signals listed alphabetically (sheet 8 of 24) signal name ball interface group page amcc proprietary 27 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 memdata00 ae12 ddr sdram 54 memdata01 ad13 memdata02 ac13 memdata03 ae11 memdata04 af10 memdata05 ae10 memdata06 ac11 memdata07 af09 memdata08 ae09 memdata09 ad10 memdata10 af08 memdata11 ae08 memdata12 ac10 memdata13 ae07 memdata14 ad08 memdata15 ad05 memdata16 ae03 memdata17 ac05 memdata18 af02 memdata19 ac03 memdata20 ac02 memdata21 aa03 memdata22 y04 memdata23 aa02 memdata24 v04 memdata25 y01 memdata26 v03 memdata27 w02 memdata28 w01 memdata29 u03 memdata30 t03 memdata31 u02 memselfref ae04 ddr sdram 54 [modectrl][irq5]dmareq1 ac12 system 59 table 5. signals listed alphabetically (sheet 9 of 24) signal name ball interface group page 28 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor [nfale][emctxd3, emc1txd1]gpio19 ac14 nand flash 58 [nfce0 ]percs0 d06 [nfce1 ][percs1 ]gpio06 c06 [nfce2 ][percs2 ]gpio07 a04 [nfce3 ][percs3 ]gpio08 b07 [nfcle][emctxd2, emc1txd0]gpio18 af14 [nfrdybusy ][emccd, emc1rxerr]gpio25 ac16 [nfren ][emcdv, emc1crsdv]gpio21 af17 [nfwen ][emctxerr, emc1txen]gpio23 af18 no ball f06 a physical ball does not exist at these ball coordinates. na no ball f07 no ball f08 no ball f09 no ball f10 no ball f11 no ball f12 no ball f13 no ball f14 no ball f15 no ball f16 no ball f17 no ball f18 no ball f19 no ball f20 no ball f21 no ball g06 no ball g07 no ball g08 no ball g09 no ball g10 no ball g11 no ball g12 no ball g13 no ball g14 no ball g15 table 5. signals listed alphab etically (sheet 10 of 24) signal name ball interface group page amcc proprietary 29 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 no ball g16 a physical ball does not exist at these ball coordinates. na no ball g17 no ball g18 no ball g19 no ball g20 no ball g21 no ball h06 no ball h07 no ball h08 no ball h09 no ball h10 no ball h11 no ball h12 no ball h13 no ball h14 no ball h15 no ball h16 no ball h17 no ball h18 no ball h19 no ball h20 no ball h21 no ball j06 no ball j07 no ball j08 no ball j09 no ball j10 no ball j11 no ball j12 no ball j13 no ball j14 no ball j15 no ball j16 no ball j17 no ball j18 no ball j19 table 5. signals listed alph abetically (sheet 11 of 24) signal name ball interface group page 30 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor no ball j20 a physical ball does not exist at these ball coordinates. na no ball j21 no ball k06 no ball k07 no ball k08 no ball k09 no ball k10 no ball k11 no ball k12 no ball k13 no ball k14 no ball k15 no ball k16 no ball k17 no ball k18 no ball k19 no ball k20 no ball k21 no ball l06 no ball l07 no ball l08 no ball l09 no ball l10 no ball l17 no ball l18 no ball l19 no ball l20 no ball l21 no ball m06 no ball m07 no ball m08 no ball m09 no ball m10 no ball m17 no ball m18 table 5. signals listed alphab etically (sheet 12 of 24) signal name ball interface group page amcc proprietary 31 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 no ball m19 a physical ball does not exist at these ball coordinates. na no ball m20 no ball m21 no ball n06 no ball n07 no ball n08 no ball n09 no ball n10 no ball n17 no ball n18 no ball n19 no ball n20 no ball n21 no ball p06 no ball p07 no ball p08 no ball p09 no ball p10 no ball p17 no ball p18 no ball p19 no ball p20 no ball p21 no ball r06 no ball r07 no ball r08 no ball r09 no ball r10 no ball r17 no ball r18 no ball r19 no ball r20 no ball r21 no ball t06 no ball t07 no ball t08 table 5. signals listed alphab etically (sheet 13 of 24) signal name ball interface group page 32 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor no ball t09 a physical ball does not exist at these ball coordinates. na no ball t10 no ball t17 no ball t18 no ball t19 no ball t20 no ball t21 no ball u06 no ball u07 no ball u08 no ball u09 no ball u10 no ball u11 no ball u12 no ball u13 no ball u14 no ball u15 no ball u16 no ball u17 no ball u18 no ball u19 no ball u20 no ball u21 no ball v06 no ball v07 no ball v08 no ball v09 no ball v10 no ball v11 no ball v12 no ball v13 no ball v14 no ball v15 no ball v16 no ball v17 table 5. signals listed alphab etically (sheet 14 of 24) signal name ball interface group page amcc proprietary 33 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 no ball v18 a physical ball does not exist at these ball coordinates. na no ball v19 no ball v20 no ball v21 no ball w06 no ball w07 no ball w08 no ball w09 no ball w10 no ball w11 no ball w12 no ball w13 no ball w14 no ball w15 no ball w16 no ball w17 no ball w18 no ball w19 no ball w20 no ball w21 no ball y06 no ball y07 no ball y08 no ball y09 no ball y10 no ball y11 no ball y12 no ball y13 no ball y14 no ball y15 no ball y16 no ball y17 no ball y18 no ball y19 no ball y20 no ball y21 table 5. signals listed alphab etically (sheet 15 of 24) signal name ball interface group page 34 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor no ball aa06 a physical ball does not exist at these ball coordinates. na no ball aa07 no ball aa08 no ball aa09 no ball aa10 no ball aa11 no ball aa12 no ball aa13 no ball aa14 no ball aa15 no ball aa16 no ball aa17 no ball aa18 no ball aa19 no ball aa20 no ball aa21 ov dd e06 power 60 ov dd e07 ov dd e08 ov dd e13 ov dd e19 ov dd e20 ov dd e21 ov dd f05 ov dd f22 ov dd g05 ov dd g22 ov dd h05 ov dd h22 ov dd l12 ov dd l15 ov dd m11 ov dd m16 ov dd n22 table 5. signals listed alphab etically (sheet 16 of 24) signal name ball interface group page amcc proprietary 35 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 pciad00 b16 pci 53 pciad01 c15 pciad02 d15 pciad03 a17 pciad04 b17 pciad05 a18 pciad06 c16 pciad07 d16 pciad08 c18 pciad09 a20 pciad10 c20 pciad11 b22 pciad12 a23 pciad13 a24 pciad14 c22 pciad15 d22 pciad16 h24 pciad17 f25 pciad18 j24 pciad19 k23 pciad20 k24 pciad21 j25 pciad22 l23 pciad23 k25 pciad24 k26 pciad25 m24 pciad26 m23 pciad27 l25 pciad28 n23 pciad29 n26 pciad30 m26 pciad31 p26 pcic0/be0 b18 pci 53 pcic1/be1 f23 pcic2/be2 f24 pcic3/be3 e26 pciclk b21 pci 53 pcidevsel d26 pci 53 pciframe g24 pci 53 table 5. signals listed alphab etically (sheet 17 of 24) signal name ball interface group page 36 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor pcignt0 /req d17 pci 53 pcignt1 l24 pcignt2 a25 pcignt3 d25 pcignt4 h25 pcignt5 e24 pciidsel g26 pci 53 pciint d20 pci 53 pciirdy e25 pci 53 pcipar c23 pci 53 pciperr d24 pci 53 pcireq0 /gnt n25 pci 53 pcireq1 b20 pcireq2 b19 pcireq3 c19 pcireq4 a22 pcireq5 h26 pcireset d19 pci 53 pciserr j23 pci 53 pcistop e23 pci 53 pcitrdy g23 pci 53 table 5. signals listed alphab etically (sheet 18 of 24) signal name ball interface group page amcc proprietary 37 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 [peraddr02]gpio05[eot3/tc3] b04 external slave peripheral 56 [peraddr03]gpio04[dmaack3] c07 [peraddr04]gpio03[dmareq3] d08 [peraddr05]gpio02[eot2/tc2] a05 [peraddr06]gpio01[dmaack2] b06 [peraddr07]gpio00[dmareq2] c08 peraddr08 d09 peraddr09 a07 peraddr10 c09 peraddr11 b08 peraddr12 d10 peraddr13 a08 peraddr14 b09 peraddr15 c10 peraddr16 c11 peraddr17 d12 peraddr18 c12 peraddr19 b11 peraddr20 b12 peraddr21 d13 peraddr22 a13 peraddr23 a12 peraddr24 a14 peraddr25 b13 peraddr26 c13 peraddr27 b14 peraddr28 a15 peraddr29 b15 peraddr30 c14 peraddr31 d14 perblast d11 external slave peripheral 56 perclk c02 external master peripheral 57 percs0 [nfce0 ]d06 external slave peripheral 56 [percs1 ][nfce1 ]gpio06 c06 [percs2 ][nfce2 ]gpio07 a04 [percs3 ][nfce3 ]gpio08 b07 [percs4 ]gpio09 b10 [percs5 ]gpio10 a10 table 5. signals listed alphab etically (sheet 19 of 24) signal name ball interface group page 38 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor perdata00 h01 external slave peripheral 56 perdata01 k04 perdata02 g01 perdata03 j03 perdata04 j04 perdata05 h03 perdata06 e01 perdata07 g03 perdata08 h04 perdata09 e02 perdata10 d01 perdata11 f03 perdata12 c01 perdata13 f04 perdata14 e03 perdata15 b01 [pererr]gpio11 e04 external master peripheral 56 peroe b03 external slave peripheral 56 perready c05 external slave peripheral 56 perr/w d05 external slave peripheral 56 perwbe0 h02 external slave peripheral 56 perwbe1 c04 psroout c26 system 59 ras k02 ddr sdram 54 [rcvrinh]holdreq y23 system 59 refen w23 system 59 rejectpkt[drvrinh1] y25 ethernet 55 table 5. signals listed alphab etically (sheet 20 of 24) signal name ball interface group page amcc proprietary 39 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 reserved r23 other 60 reserved r24 reserved u23 reserved v23 reserved w25 reserved w26 reserved y26 reserved ab23 reserved ab24 reserved ac20 reserved ac21 reserved ac24 reserved ad20 reserved ad21 reserved ad22 reserved ad23 reserved ae22 reserved ae23 reserved ae26 reserved af23 reserved af24 sagnd af15 power 60 sav dd ae14 scpclkout[iic1sclk] u24 serial peripheral (spi) 58 scpdi[iic1sdata] v25 scpdo t23 table 5. signals listed alphab etically (sheet 21 of 24) signal name ball interface group page 40 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor sv dd p05 power 60 sv dd r11 sv dd r16 sv dd t12 sv dd t15 sv dd w05 sv dd w22 sv dd y05 sv dd y22 sv dd aa05 sv dd aa22 sv dd ab06 sv dd ab07 sv dd ab08 sv dd ab14 sv dd ab19 sv dd ab20 sv dd ab21 sv ref1 w04 ddr sdram 54 sv ref2a p03 sv ref2b ae06 sysclk ae19 system 59 syserr ab01 system 59 sysreset ae18 system 59 tck b05 jtag 58 tdi c17 jtag 58 tdo c21 jtag 58 testen a03 system 59 tmrclk1 ad11 system 59 tmrclk2 ad25 system 59 tms d02 jtag 58 [trcbs0]gpio49 ae21 trace 60 [trcbs1]gpio50 ac25 [trcbs2]gpio51 aa24 trcclk ac19 trace 60 table 5. signals listed alphab etically (sheet 22 of 24) signal name ball interface group page amcc proprietary 41 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 [trces0]gpio52 y03 trace 60 [trces1]gpio53 aa04 [trces2]gpio54 ab03 [trces3]gpio55 ab04 [trces4]gpio56 af22 [trcts0]gpio57 ac22 trace 60 [trcts1]gpio58 ae24 [trcts2]gpio59 ad04 [trcts3]gpio60 ad06 [trcts4]gpio61 ac09 [trcts5]gpio62 ad12 [trcts6]gpio63 ae15 trst d07 jtag 58 [uart0_cts /uart3_rx]gpio36 v26 uart peripheral 57 [uart0_rts/ uart3_tx]gpio37 r26 uart0_rx t25 uart0_tx p25 [uart0_dcd /uart1_cts/ uart2_tx]gpio34 r25 [uart0_dsr /uart1_rts/ uart2_rx]gpio35 u26 [uart0_dtr /uart1_tx]gpio38 n24 [uart0_ri /uart1_rx]gpio39 p24 uartserclk p23 table 5. signals listed alphab etically (sheet 23 of 24) signal name ball interface group page 42 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor v dd e05 power 60 v dd e10 v dd e11 v dd e12 v dd e15 v dd e16 v dd e17 v dd e22 v dd k05 v dd k22 v dd l05 v dd l22 v dd m05 v dd m22 v dd m14 v dd n12 v dd p15 v dd r05 v dd r13 v dd r22 v dd t05 v dd t22 v dd u05 v dd u22 v dd ab05 v dd ab10 v dd ab11 v dd ab12 v dd ab15 v dd ab16 v dd ab17 v dd ab22 we k01 ddr sdram 54 table 5. signals listed alphab etically (sheet 24 of 24) signal name ball interface group page amcc proprietary 43 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 in the following table, only the primary (default) signal name is shown for each pin. multiplexed or multifunction signals are marked with an asterisk (*). to determine what signals or functions are mult iplexed on those pins, look up the primary signal name in table 5, signals listed alphabetically . table 6. signals listed by ba ll assignment (sheet 1 of 7) ball signal name ball signal name ball signal name ball signal name a01 gnd b01 perdata15 c01 perdata12 d01 perdata10 a02 gnd b02 gnd c02 perclk d02 tms a03 testen b03 peroe c03 gnd d03 irq0* a04 gpio07* b04 gpio05* c04 perwbe1 d04 gnd a05 gpio02* b05 tck c05 perready d05 perr/w a06 gnd b06 gpio01* c06 gpio06* d06 percs0 * a07 peraddr09 b07 gpio08* c07 gpio04* d07 trst a08 peraddr13 b08 peraddr11 c08 gpio00* d08 peraddr04* a09 gnd b09 peraddr14 c09 peraddr10 d09 peraddr08 a10 percs5 * b10 gpio09* c10 peraddr15 d10 peraddr12 a11 gnd b11 peraddr19 c11 peraddr16 d11 perblast a12 peraddr23 b12 peraddr20 c12 peraddr18 d12 peraddr17 a13 peraddr22 b13 peraddr25 c13 peraddr26 d13 peraddr21 a14 peraddr24 b14 peraddr27 c14 peraddr30 d14 peraddr31 a15 peraddr28 b15 peraddr29 c15 pciad01 d15 pciad02 a16 gnd b16 pciad00 c16 pciad06 d16 pciad07 a17 pciad03 b17 pciad04 c17 tdi d17 pcignt0 /req a18 pciad05 b18 pcic0/be0 c18 pciad08 d18 gpio47* a19 irq9* b19 pcireq2 c19 pcireq3 d19 pcireset a20 pciad09 b20 pcireq1 c20 pciad10 d20 pciint a21 gnd b21 pciclk c21 tdo d21 gnd a22 pcireq4 b22 pciad11 c22 pciad14 d22 pciad15 a23 pciad12 b23 extreset c23 pcipar d23 gnd a24 pciad13 b24 gpio46* c24 gnd d24 pciperr a25 pcignt2 b25 gnd c25 halt * d25 pcignt3 a26 gnd b26 gnd c26 psroout d26 pcidevsel 44 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor e01 perdata06 f01 gnd g01 perdata02 h01 perdata00 e02 perdata09 f02 gpio42* g02 irq3* h02 perwbe0 e03 perdata14 f03 perdata11 g03 perdata07 h03 perdata05 e04 gpio11* f04 perdata13 g04 gpio41* h04 perdata08 e05 v dd f05 ov dd g05 ov dd h05 ov dd e06 ov dd f06 no ball g06 no ball h06 no ball e07 ov dd f07 no ball g07 no ball h07 no ball e08 ov dd f08 no ball g08 no ball h08 no ball e09 gnd f09 no ball g09 no ball h09 no ball e10 v dd f10 no ball g10 no ball h10 no ball e11 v dd f11 no ball g11 no ball h11 no ball e12 v dd f12 no ball g12 no ball h12 no ball e13 ov dd f13 no ball g13 no ball h13 no ball e14 gnd f14 no ball g14 no ball h14 no ball e15 v dd f15 no ball g15 no ball h15 no ball e16 v dd f16 no ball g16 no ball h16 no ball e17 v dd f17 no ball g17 no ball h17 no ball e18 gnd f18 no ball g18 no ball h18 no ball e19 ov dd f19 no ball g19 no ball h19 no ball e20 ov dd f20 no ball g20 no ball h20 no ball e21 ov dd f21 no ball g21 no ball h21 no ball e22 v dd f22 ov dd g22 ov dd h22 ov dd e23 pcistop f23 pcic1/be1 g23 pcitrdy h23 gpio45* e24 pcignt5 f24 pcic2/be2 g24 pciframe h24 pciad16 e25 pciirdy f25 pciad17 g25 gpio44* h25 pcignt4 e26 pcic3/be3 f26 gnd g26 pciidsel h26 pcireq5 table 6. signals listed by ba ll assignment (sheet 2 of 7) ball signal name ball signal name ball signal name ball signal name amcc proprietary 45 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 j01 dm2 k01 we l01 gnd m01 ecc2 j02 cas k02 ras l02 ecc6 m02 ecc3 j03 perdata03 k03 dqs2 l03 dm3 m03 ecc7 j04 perdata04 k04 perdata01 l04 gnd m04 dqs3 j05 gnd k05 v dd l05 v dd m05 v dd j06 no ball k06 no ball l06 no ball m06 no ball j07 no ball k07 no ball l07 no ball m07 no ball j08 no ball k08 no ball l08 no ball m08 no ball j09 no ball k09 no ball l09 no ball m09 no ball j10 no ball k10 no ball l10 no ball m10 no ball j11 no ball k11 no ball l11 gnd m11 ov dd j12 no ball k12 no ball l12 ov dd m12 gnd j13 no ball k13 no ball l13 gnd m13 gnd j14 no ball k14 no ball l14 gnd m14 v dd j15 no ball k15 no ball l15 ov dd m15 gnd j16 no ball k16 no ball l16 gnd m16 ov dd j17 no ball k17 no ball l17 no ball m17 no ball j18 no ball k18 no ball l18 no ball m18 no ball j19 no ball k19 no ball l19 no ball m19 no ball j20 no ball k20 no ball l20 no ball m20 no ball j21 no ball k21 no ball l21 no ball m21 no ball j22 gnd k22 v dd l22 v dd m22 v dd j23 pciserr k23 pciad19 l23 pciad22 m23 pciad26 j24 pciad18 k24 pciad20 l24 pcignt1 m24 pciad25 j25 pciad21 k25 pciad23 l25 pciad27 m25 gnd j26 gnd k26 pciad24 l26 gnd m26 pciad30 table 6. signals listed by ba ll assignment (sheet 3 of 7) ball signal name ball signal name ball signal name ball signal name 46 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor n01 banksel3 p01 memaddr00 r01 banksel2 t01 gnd n02 ecc1 p02 ecc0 r02 banksel1 t02 memaddr02 n03 ecc4 p03 sv ref2a r03 memaddr10 t03 memdata30 n04 ecc5 p04 memaddr01 r04 banksel0 t04 memaddr03 n05 gnd p05 sv dd r05 v dd t05 v dd n06 no ball p06 no ball r06 no ball t06 no ball n07 no ball p07 no ball r07 no ball t07 no ball n08 no ball p08 no ball r08 no ball t08 no ball n09 no ball p09 no ball r09 no ball t09 no ball n10 no ball p10 no ball r10 no ball t10 no ball n11 gnd p11 gnd r11 sv dd t11 gnd n12 v dd p12 gnd r12 gnd t12 sv dd n13 gnd p13 gnd r13 v dd t13 gnd n14 gnd p14 gnd r14 gnd t14 gnd n15 gnd p15 v dd r15 gnd t15 sv dd n16 gnd p16 gnd r16 sv dd t16 gnd n17 no ball p17 no ball r17 no ball t17 no ball n18 no ball p18 no ball r18 no ball t18 no ball n19 no ball p19 no ball r19 no ball t19 no ball n20 no ball p20 no ball r20 no ball t20 no ball n21 no ball p21 no ball r21 no ball t21 no ball n22 ov dd p22 gnd r22 v dd t22 v dd n23 pciad28 p23 uartserclk r23 reserved t23 scpdo n24 gpio38* p24 gpio39* r24 reserved t24 iic0sdata n25 pcireq0 /gnt p25 uart0_tx* r25 gpio34* t25 uart0_rx n26 pciad29 p26 pciad31 r26 gpio37* t26 gnd table 6. signals listed by ba ll assignment (sheet 4 of 7) ball signal name ball signal name ball signal name ball signal name amcc proprietary 47 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 u01 memaddr04 v01 gnd w01 memdata28 y01 memdata25 u02 memdata31 v02 memaddr05 w02 memdata27 y02 memaddr08 u03 memdata29 v03 memdata26 w03 memaddr07 y03 gpio52* u04 memaddr06 v04 memdata24 w04 sv ref1 y04 memdata22 u05 v dd v05 gnd w05 sv dd y05 sv dd u06 no ball v06 no ball w06 no ball y06 no ball u07 no ball v07 no ball w07 no ball y07 no ball u08 no ball v08 no ball w08 no ball y08 no ball u09 no ball v09 no ball w09 no ball y09 no ball u10 no ball v10 no ball w10 no ball y10 no ball u11 no ball v11 no ball w11 no ball y11 no ball u12 no ball v12 no ball w12 no ball y12 no ball u13 no ball v13 no ball w13 no ball y13 no ball u14 no ball v14 no ball w14 no ball y14 no ball u15 no ball v15 no ball w15 no ball y15 no ball u16 no ball v16 no ball w16 no ball y16 no ball u17 no ball v17 no ball w17 no ball y17 no ball u18 no ball v18 no ball w18 no ball y18 no ball u19 no ball v19 no ball w19 no ball y19 no ball u20 no ball v20 no ball w20 no ball y20 no ball u21 no ball v21 no ball w21 no ball y21 no ball u22 v dd v22 gnd w22 sv dd y22 sv dd u23 reserved v23 reserved w23 refen y23 holdreq* u24 scpclkout* v24 holdpri* w24 gpio32 y24 gpio28 u25 iic0sclk v25 scpdi* w25 reserved y25 rejectpkt* u26 gpio35* v26 gpio36* w26 reserved y26 reserved table 6. signals listed by ba ll assignment (sheet 5 of 7) ball signal name ball signal name ball signal name ball signal name 48 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor aa01 gnd ab01 syserr ac01 gnd ad01 memaddr11 aa02 memdata23 ab02 memaddr09 ac02 memdata20 ad02 memaddr12 aa03 memdata21 ab03 gpio54* ac03 memdata19 ad03 gnd aa04 gpio53* ab04 gpio55* ac04 gnd ad04 gpio59* aa05 sv dd ab05 v dd ac05 memdata17 ad05 memdata15 aa06 no ball ab06 sv dd ac06 dqs8 ad06 gpio60* aa07 no ball ab07 sv dd ac07 gnd ad07 dm1 aa08 no ball ab08 sv dd ac08 dqs1 ad08 memdata14 aa09 no ball ab09 gnd ac09 trcts4* ad09 dqs0 aa10 no ball ab10 v dd ac10 memdata12 ad10 memdata09 aa11 no ball ab11 v dd ac11 memdata06 ad11 tmrclk1 aa12 no ball ab12 v dd ac12 irq5* ad12 gpio62* aa13 no ball ab13 gnd ac13 memdata02 ad13 memdata01 aa14 no ball ab14 sv dd ac14 gpio19* ad14 gpio16* aa15 no ball ab15 v dd ac15 emctxclk* ad15 gpio22* aa16 no ball ab16 v dd ac16 gpio25* ad16 gpio20* aa17 no ball ab17 v dd ac17 gpio15* ad17 av dd aa18 no ball ab18 gnd ac18 emcmdio ad18 gpio14* aa19 no ball ab19 sv dd ac19 trcclk ad19 gpio12* aa20 no ball ab20 sv dd ac20 reserved ad20 reserved aa21 no ball ab21 sv dd ac21 reserved ad21 reserved aa22 sv dd ab22 v dd ac22 gpio57* ad22 reserved aa23 gpio31* ab23 reserved ac23 gnd ad23 reserved aa24 gpio51* ab24 reserved ac24 reserved ad24 gnd aa25 gpio30* ab25 gpio29* ac25 gpio50* ad25 tmrclk2 aa26 gnd ab26 gpio33 ac26 gpio26* ad26 gpio27* table 6. signals listed by ba ll assignment (sheet 6 of 7) ball signal name ball signal name ball signal name ball signal name amcc proprietary 49 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 ae01 gnd af01 gnd ae02 gnd af02 memdata18 ae03 memdata16 af03 ba0 ae04 memselfref af04 ba1 ae05 dm0 af05 clken ae06 sv ref2b af06 gnd ae07 memdata13 af07 dm8 ae08 memdata11 af08 memdata10 ae09 memdata08 af09 memdata07 ae10 memdata05 af10 memdata04 ae11 memdata03 af11 gnd ae12 memdata00 af12 memclkout0 ae13 memclkout0 af13 gpio17* ae14 sav dd af14 gpio18* ae15 gpio63* af15 sagnd ae16 emcmdclk af16 gnd ae17 agnd af17 gpio21* ae18 sysreset af18 gpio23* ae19 sysclk af19 emcrxclk ae20 gpio13* af20 gpio24* ae21 gpio49* af21 gnd ae22 reserved af22 gpio56* ae23 reserved af23 reserved ae24 gpio58* af24 reserved ae25 gnd af25 gnd ae26 reserved af26 gnd table 6. signals listed by ba ll assignment (sheet 7 of 7) ball signal name ball signal name ball signal name ball signal name 50 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor signal descriptions the ppc440gr embedded controller is packaged in a 456-ball enhanced plastic ball grid array (e-pbga). the following tables describe the package level pinout. in the table ?signal functional description? on page 53, each i/o signal is listed along with a short description of its function. active-low signals (for example, ras ) are marked with an overline. please see ?signals listed alphabetically? on page 19 for the pin (ball) number to which each signal is assigned. multiplexed signals some signals are multiplexed on the same pin so that the pin can be used for different functions. in most cases, the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same pin. if you need to know what, if any, signals are multiple xed with a particular signal, look up the name in ?signals listed alphabetically? on page 19. it is expected that in any single app lication a particular pin will always be programmed to serve the same function. the flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. the circuit type for multiplexed signals is shown as ?multiplex.? the actual circuit type is the same as the primary signal. note: signals multiplexed wit gpio default to gpio receiver s and float after reset. in itialization so ftware must configure the gpio registers for the desired function as described in the gpio chapter of the user?s manual. any of these signals requiring a particular state prior to runni ng initialization code must be terminated with pull ups or pull downs. multipurpose signals in addition to multiplexing, some pins are also multi- purpose. for example, the ebc peripheral controller address pins (peraddr) are used as outputs by the ppc440gr to broadcast an address to external slave devices when the ppc440gr has control of the external bus. when during the course of normal chip operation an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the ebc in the ppc440gr. in this example, the pins are also bidirectional, serving both as inputs table 7. pin summary group no. of pins signal pins, non-multiplexed 221 signal pins, multiplexed 62 total signal pins 283 av dd 1 sav dd 1 sagnd 1 agnd 1 ov dd 18 sv dd 18 v dd 32 gnd 80 total power pins 152 reserved 21 total pins 456 amcc proprietary 51 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 and outputs. multimode signals in some cases (for example, ethernet) the function of a pin may vary with different modes of operation. when a pin has multiple signal names assigned to distinguish different modes of operation, all of the names are shown. strapping pins one group of pins is used as strapped inputs during syst em reset. these pins function as strapped inputs only during reset and are used for other functions during no rmal operation (see ?strapping? on page 85). note that these are not multiplexed pins since the function of the pins is not programmable. reserved pins the balls marked reserved on this chip are not functional. however, most of the reserved balls cannot be left unconnected. connect the balls shown in table 8 as indicated: table 8. non-functional ball connections ball connection r23 gnd r24 gnd u23 gnd v23 gnd w25 gnd w26 gnd y26 gnd ab23 gnd ab24 gnd ac20 gnd ac21 gnd ac24 gnd ad20 gnd ad21 gnd ad22 gnd ad23 gnd ae22 do not connect ae23 gnd ae26 gnd af23 do not connect af24 gnd 52 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor unused i/os termination of unused receivers is generally required; howe ver there are some exceptions that reduce or eliminate the need for termination. signals multiplexed with gpio: by default after reset, signals shared with gpio pins are conf igured as gpio receivers. termination however is not needed if the gpio during initialization are configured as outputs. to configure as drivers, se t and clear the appropriate bits in the gpiox_odr, gpiox_tcr and gpiox_or registers as de scribed in the gpio chapter of the user?s manual. pci: when the pci bridge is unused, configure the pci controller to park on the bus by pulling the pcireq0 [gnt] signal low. parking forces the plb3 to pci bridge to actively drive pciad31:0 and pcic3:0[be3:0]. the remaining pci control signals must be terminated as follows: ? disable the internal pci arbiter and enable pci synchronous mode (see iic boot strap chapter in the user?s manual). ( note: synchronous mode is not suppor ted when operating the pci bus. this mode should only be used for terminating an unused pci interface). ? individually connect pciserr, pciperr, pcitrdy, and pcistop through 3k resistors to +3.3v. ? terminate pcireq1:5 through 3k resistors to +3.3v. ? terminate pcireq0[gnt] through a 1k resistor to gnd. ddr: when ecc is not used, no termination is needed for unused ecc signals (ecc0:7, dm8, and ds8). usb host: when the usb host interface is not used, a clock is still requir ed for usb1clk in order to rese t the usb host. if the usb host does not reset, it can interfere with the internal plb3 and opb buses. the usb host signals must be terminated as follows: ? a clock must be connected to usb1clk. the clock can be any frequency from 32khz to 48mhz. ? usb1hostxcvr and usb1hostxcv signals must be pulled down. usb device: the usb device requires a subset of the usb signals to be terminated. ? usb2ls0[drvrlnh1][rejectpkt] must be pulled by unless used as a packet reject input. ? usb2d10:7, usb1devxcvr, usb1devxcvr and usb2clk signals must be pulled down. smii0, rmii0 or mii: ? configure emac0 to use internal clocks by sett ing sdr0_mfr[e0cs]=1 and reset emac0 by setting emac0_mr0[srst]=1. ? no pull ups or pull downs required smii1, rmii1 or mii: ? configure emac1 to use internal clocks by sett ing sdr0_mfr[e1cs]=1 and reset emac1 by setting emac0_mr1[srst]=1. ? no pull ups or downs required. oddities: tmrclk2 must be connected to a clock to ensure reset of in ternal logic. it can be connected to any available clocks in the frequency range of 32khz to 100mhz. amcc proprietary 53 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 table 9. signal functional description (sheet 1 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v ) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes pci interface pciad00:31 address/data bus (bidirectional). i/o 3.3v pci pcic0:3/be0:3 pci command/byte enables . i/o 3.3v pci pciclk provides timing to the pci inte rface for pci transactions. i 3.3v pci 5 pcidevsel indicates the driving device has decoded its address as the target of the current access. (pci 2.2 specification requires 8.2k pull up on host system) i/o 3.3v pci pciframe driven by the current master to indicate beginning and duration of an access. (pci 2.2 specification requires 8.2k pull up on host system) i/o 3.3v pci pcignt1 /req indicates that the specified agent is granted access to the bus. when the internal arbiter is enabled, output is pcignt0 . when the internal arbiter is disabled, output is req . o 3.3v pci pcignt2:6 indicates that the specified agent is granted access to the bus. o 3.3v pci pciidsel used as a chip select during configuration read and write transactions. i 3.3v pci pciint level sensitive pci interrupt. o 3.3v pci pciirdy indicates initiating agent?s ability to complete the current data phase of the transaction. (pci 2.2 specification requires 8.2k pull up on host system) i/o 3.3v pci pcipar even parity. i/o 3.3v pci pciperr reports data parity errors duri ng all pci transactions except a special cycle. (pci 2.2 specification requires 8.2k pull up on host system) i/o 3.3v pci pcireq0 /gnt indicates to the pci arbiter that the specified agent wishes to use the bus. when the internal arbiter is enabled, input is pcireq0 . when internal arbiter is disabled, input is gnt . i 3.3v pci 4 pcireq1:5 an indication to the pci arbiter that the specified agent wishes to use the bus. i 3.3v pci 4 pcireset brings pci device registers and logic to a consistent state. o 3.3v pci pciserr reports address parity errors, data parity errors on the special cycle command, or other catastrophic system errors. (pci 2.2 specification requires 8.2k pull up on host system) i/o 3.3v pci pcistop indicates the current target is requesting the master to stop the current transaction. (pci 2.2 specification requires 8.2k pull up on host system) i/o 3.3v pci pcitrdy i ndicates the target agent?s ability to complete the current data phase of the transaction. (pci 2.2 specification requires 8.2k pull up on host system) i/o 3.3v pci 54 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor ddr sdram interface ba0:1 bank address supporting up to four internal banks. o 2.5v sstl_2 banksel0:3 selects up to four external ddr sdram banks. o 2.5v sstl_2 cas column address strobe. o 2.5v sstl_2 clken clock enable. o 2.5v sstl_2 dm0:3 dm8 memory write data byte lane masks. dm8 is the byte lane mask for the ecc byte lane. o 2.5v sstl_2 dqs0:3 dqs8 byte lane data strobe. dqs8 is the data strobe for the ecc byte lane. i/o 2.5v sstl_2 ecc0:7 ecc check bits 0:7. i/o 2.5v sstl_2 memaddr00:12 memory address bus. o 2.5v sstl_2 memclkout0 memclkout0 subsystem clock. o 2.5v sstl_2 diff driver memdata00:31 memory data bus. i/o 2.5v sstl_2 memselfref self refresh. i 3.3v tolerant 2.5v cmos 5 ras row address strobe. o 2.5v sstl_2 we write enable. o 2.5v sstl_2 s vref1 sstl reference voltage. i volt ref receiver s vref2a:b supplemental sstl reference voltage. i volt ref pin (supplemental) table 9. signal functional description (sheet 2 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v ) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes amcc proprietary 55 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 ethernet interface emccd, emc1rxerr mii: collision detection. rmii1: receive error. i/o 3.3v tolerant 2.5v cmos emccrs, emc0crsdv mii: carrier sense. rmii0: carrier sense data valid. i/o 3.3v tolerant 2.5v cmos emcdv, emc1crsdv mii: data valid. rmii1: carrier sense data valid. i/o 3.3v tolerant 2.5v cmos emcmdclk mii: management data clock. o 3.3v tolerant 2.5v cmos emcmdio mii: transfer command and status information between mii and phy. i/o 3.3v tolerant 2.5v cmos emcrxclk mii: receive clock. i/o 3.3v tolerant 2.5v cmos emcrxd0:1, emc0rxd0:1 emc0:1rxd mii: receive data. rmii0: receive data. smii0 and smii1: receive data. i/o 3.3v tolerant 2.5v cmos emcrxd2:3, emc1rxd0:1 mii: receive data. rmii1: receive data. i/o 3.3v tolerant 2.5v cmos emcrxerr, emc0rxerr mii: receive error. rmii0: receive error. i/o 3.3v tolerant 2.5v cmos emctxclk, emcrefclk mii: transmit clock. rmii: reference clock (125mhz) smii: reference clock (50mhz). i 3.3v tolerant 2.5v cmos emctxd0:1, emc0txd0:1 emc0:btxd mii: transmit data. rmii0: transmit data. smii0 and smii1: transmit data. i/o 3.3v tolerant 2.5v cmos emctxd2:3, emc1txd0:1 mii: transmit data. rmii1: transmit data. i/o 3.3v tolerant 2.5v cmos emctxen, emc0txen, emcsync mii: transmit data enabled. rmii0: transmit data enabled. smii: sync signal. note: redrive emcsync when driving more than one load. emcsync is a weak driver. o 3.3v tolerant 2.5v cmos emctxerr, emc1txen mii: transmit error. rmii1: transmit data enabled. i/o 3.3v tolerant 2.5v cmos rejectpkt external request to reject a packet. i 3.3v tolerant 2.5v cmos table 9. signal functional description (sheet 3 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v ) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 56 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor external slave peripheral interface dmaack0:3 used by the ppc440gr to indicate that data transfers have occurred. o multiplex dmareq0:3 used by slave peripherals to indicate they are prepared to transfer data. i multiplex 1 eot0:3/tc0:3 end of transfer/terminal count. i/o multiplex 1 peraddr02:07 peripheral address bus used by ppc440gr when not in external master mode, otherwise used by external master. i/o 3.3v lvttl 1, 2 peraddr08:31 peripheral address bus used by ppc440gr when not in external master mode, otherwise used by external master. i/o 3.3v lvttl perblast used by either the peripheral controller, dma controller, or external master to indicates the last transfer of a memory access. i/o 3.3v lvttl 1, 4 percs0:5 external peripheral devic e select. o 3.3v lvttl 2 perdata00:15 peripheral data bus used by ppc440gr when not in external master mode, otherwise used by external master. note: perdata00 is the most significant bit (msb) on this bus. i/o 3.3v lvttl 1 peroe used by either peripheral controller or dma controller depending upon the type of transfer involved. when the ppc440gr is the bus master, it enables the selected device to drive the bus. o3.3v lvttl 2 perready used by a peripheral slave to i ndicate it is ready to transfer data. i3.3v lvttl perr/w used by the ppc440gr when not in external master mode, as output by either the peripheral controller or dma controller depending upon the type of transfer involved. high indicates a read from memory, low indicates a write to memory. otherwise, it used by the external master as an input to indicate the direction of transfer. i/o 3.3v lvttl 1, 2 perwbe0:1 external peripheral data bus by te enables. i/o 3.3v lvttl 1, 2 pererr external error. used as an input to record external slave peripheral errors. i/o 3.3v lvttl 1 table 9. signal functional description (sheet 4 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v ) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes amcc proprietary 57 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 external master peripheral interface busreq bus request. used when the ppc440gr needs to regain control of peripheral interface from an external master. o multiplex extack external acknowledgement. used by the ppc440gr to indicate that a data transfer occurred. o multiplex extreq external request. used by an external master to indicate it is prepared to transfer data. i multiplex 1 extreset peripheral reset. used by an external master and by synchronous peripheral slaves. o3.3v lvttl holdack hold acknowledge. used by the ppc440gr to transfer ownership of peripheral bus to an external master. o multiplex holdreq hold request. used by an external master to request ownership of the peripheral bus. i multiplex 1, 5 holdpri hold primary. used by an external master to indicate the priority of a given external master tenure. i multiplex perclk peripheral clock. used by an external master and by synchronous peripheral slaves. o3.3v lvttl uart peripheral interface uartserclk serial clock input that provides an alternative to the internally generated serial clock. used in cases where the allowable internally generated clock rates are not satisfactory. i 3.3v lvttl 1, 4 uartn_rx uart receive data. i 3.3v lvttl 1, 4 uartn_tx uart transmit data. o 3.3v lvttl uartn_dcd uart data carrier detect. i 3.3v lvttl 6 uartn_dsr uart data set ready. i 3.3v lvttl 6 uartn_cts uart clear to send. i 3.3v lvttl 1, 6 uartn_dtr uart data terminal ready. o 3.3v lvttl uartn_rts uart request to send. o 3.3v lvttl uartn_ri uart ring indicator. i 3.3v lvttl 1 iic peripheral interface iic0sclk iic0 serial clock. i/o 3.3v lvttl 1, 2 iic0sdata iic0 serial data. i/o 3.3v lvttl 1, 2 iic10sclk iic1 serial clock. i/o multiplex 2 iic1sdata iic1 serial data. i/o multiplex 2 table 9. signal functional description (sheet 5 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v ) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 58 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor nand flash interface nfale address latch enable. o multiplex nfce0:3 chip enable (multiplexed with the percs0:3 signals). o multiplex nfcle command latch enable. o multiplex nfrdybusy ready/busy. indicates status of device duri ng program erase or page read. this signal is wire-or connect ed from all nand flash devices. i multiplex nfren read enable strobe. o multiplex nfwen write enable strobe. o multiplex serial peripheral interface scpclkout clock output. o 3.3v lvttl 2 scpdi data in. i 3.3v lvttl 2 scpdo data output. o 3.3v lvttl 2 interrupts interface irq0:4 external interrupt requests 0 through 4. i/o 3.3v lvttl 1 irq5 external interrupt request 5. i 3.3v tolerant 2.5v cmos 1 irq6:9 external interrupt requests 6 through 9. i/o 3.3v lvttl 1 jtag interface tck test clock. i 3.3v lvttl w/pull-up 1 tdi test data in. i 3.3v lvttl w/pull-up 4 tdo test data out. o 3.3v lvttl tms test mode select. i 3.3v lvttl w/pull-up 1 trst test reset. note: must be asserted low during a power-on system reset in order to reset the jtag interface. if the jtag interface is not reset, the processor may not boot. i 3.3v lvttl w/pull-up 5 table 9. signal functional description (sheet 6 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v ) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes amcc proprietary 59 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 system interface sysclk main system clock input. clock 3.3v lvttl syserr set to 1 when a machine check is generated. o 3.3v tolerant 2.5v cmos sysreset main system reset. external logi c can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset. a system reset can also be initiated by software. implemented as an open-drain output (two states; 0 or open circuit). i/o 3.3v tolerant 2.5v cmos 1, 2 halt halt from external debugger. i 3.3v lvttl 1, 2 tmrclk1 processor timer external input clock. i 3.3v tolerant 2.5v cmos tmrclk2 this signal must be connected to a clock. it can be connected to any available clocking si gnal in the frequency range of 32khz to 100mhz including tmrclk1. i 3.3v tolerant 2.5v cmos gpio00:63 general purpose i/o 0 through 63. to access these functions, software must set dcr register bits. i/o multiplex testen test enable. i multiplex 3 rcvrinh receiver inhibit. active only w hen testen is active. used for manufacturing test only. i multiplex modectrl mode control. active only when testen is active. used for manufacturing test only. i multiplex leaktest leakage test. active only when testen is active. used for manufacturing test only. i multiplex refen reference enable. active only w hen testen is active. used for manufacturing test only. i multiplex drvrinh1:2 driver inhibit. active only w hen testen is active. used for manufacturing test only. i 3.3v tolerant 2.5v cmos psroout module characterization and screening. o perf screen ring osc 1, 3 table 9. signal functional description (sheet 7 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v ) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 60 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor trace interface trcbs0:2 trace branch execution status. i/o 3.3v tolerant 2.5v cmos trcclk trace data capture clock, runs at 1/4 the frequency of the processor. o 3.3v tolerant 2.5v cmosl trces0:4 trace execution status is pr esented every fourth processor clock cycle. i/o 3.3v lvttl trcts0:6 additional information on trace execution and branch status. i/o 3.3v tolerant 2.5v cmos power v dd 1.5v supply?logic voltage. na na ov dd 3.3v supply?i/o (except ddr sdram, ethernet). na na sv dd 2.5v supply?sdram, ethernet. na na gnd ground. na na av dd 1.5v?filtered voltage for system plls (analog). na na agnd pll (analog) voltage ground. na na sav dd 1.5v?filtered voltage for memory pll (analog). na na sagnd pll (analog) memory voltage ground. na na other reserved to avoid noise pickup problems, most of these balls must be connected in the board design as shown table 8 on page 51. na na table 9. signal functional description (sheet 8 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v ) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes amcc proprietary 61 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 device characteristics table 10. absolute maximum ratings the absolute maximum ratings bel ow are stress ratings only. operation at or beyond thes e maximum ratings can cause permanent damage to the device. none of the performance spec ification contained in this document are guaranteed when operating at these maximum ratings. characteristic symbol value unit notes supply voltage (internal logic) v dd 0 to +1.65 v 1 supply voltage (i/o, except sdram, ethernet) ov dd 0 to +3.6 v 1 supply voltage (sdram, ethernet) sv dd 0 to +2.7 v pll supply voltage av dd 0 to +1.65 v 2 sdram pll supply voltage sav dd 0 to +1.65 v 2 input voltage (3.3v lvttl receivers) v in 0 to +3.6 v storage temperature range t stg -55 to +150 c case temperature under bias t c -40 to +120 c2 notes: 1. if ov dd 0.4v, it is required that v dd 0.4v. supply excursions not meeting this criter ia must be limited to less than 25ms duration during each power up or power down event. 2. this value is not a spec ification of the operational temperature range, it is a stress rating only. 62 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor table 11. recommended dc operating conditions (sheet 1 of 2) device operation beyond the conditions specified is no t recommended. extended operation beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes logic supply voltage v dd +1.4 +1.5 +1.6 v 4 i/o supply voltage ov dd +3.0 +3.3 +3.6 v 4 sdram supply voltage sv dd +2.3 +2.5 +2.7 v 4 pll supply voltages av dd +1.4 +1.5 +1.6 v 3, 4 sdram pll voltage sav dd +1.4 +1.5 +1.6 v 3, 4 ddr sdram reference voltage sv ref +1.15 +1.25 +1.35 v 2 input logic high (2.5v sstl) v ih sv ref +0.18 sv dd +0.3 v input logic high (2.5v cmos, 3.3v tolerant receiver) 1.7 ??? v input logic high (3.3v pci) 0.5ov dd ov dd +0.5 v1 input logic high (3.3v lvttl) +2.0 +3.6 v input logic low (2.5v sstl) v il -0.3 sv ref -0.18 v input logic low (2.5v cmos, 3.3v tolerant receiver) 0.7 v input logic low (3.3v pci) -0.5 0.35ov dd v1 input logic low (3.3v lvttl) 0 +0.8 v output logic high (2.5v sstl) v oh +1.95 sv dd v output logic high (2.5v cmos, 3.3v tolerant receiver) 2.0 v output logic high (3.3v pci) 0.9ov dd ov dd v1 output logic high (3.3v lvttl) +2.4 ov dd v output logic low (2.5v sstl) v ol 00.55v output logic low (2.5v cmos, 3.3v tolerant receiver) 0.4 v output logic low (3.3v pci) 0.1ov dd v1 output logic low (3.3v lvttl) 0 +0.4 v input leakage current (no pull-up or pull-down) i il1 00 a input leakage current for pull-down i il2 0 (lpdl) 200 (mpul) a input leakage current for pull-up i il3 -150 (lpdl) 0 (mpul) a input max allowable overshoot (3.3v lvttl) v imao +3.9 v 4, 5 input max allowable undershoot (3.3v lvttl) v imau -0.6 v 4, 5 output max allowable overshoot (3.3v lvttl) v omao +3.9 v 4, 5 output max allowable undershoot (3.3v lvttl) v omau3 -0.6 v 4, 5 amcc proprietary 63 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 figure 4. overshoot waveform case temperature: 333mhz and 400mhz parts in any package 533mhz parts in any package 667mhz parts t c -40 -40 -40 -90 -100 +85 c notes: 1. pci drivers meet pci specifications. 2. sv ref = sv dd /2 3. the analog voltages used for the on-chip p lls can be derived from the logic voltage, but must be filtered before entering the ppc440gr. see ?absolute maximum ratings? on page 61. 4. overshoot and undershoot volta ges are for 10% duty cycle. 5. the time for overshoot or undershoot is time above ov dd and the time below 0v. table 11. recommended dc operating conditions (sheet 2 of 2) device operation beyond the conditions specified is no t recommended. extended operation beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes ac undershoot (v) t os t os dc overshoot (v) dc undershoot (v) t cyc ac overshoot (v) 64 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor power sequencing startup sequencing of the power supply voltages is not required. however, a power-down cycl e must complete (ov dd and v dd are below +0.4v) before a new power-up cycle is started. analog voltage filter the analog voltages used for the on-chip plls can be derived from the logic voltage, but must be filtered before entering the ppc440gr. a separate filter, as shown below, is recommended for each voltage. ? the filter should keep the av dd -agnc (sagnd-sagnd) compression/expansion due to noise less than + 50 mv. ? all wire lengths of the filter circuit should be kept as short as po ssible to minimize coupling from other signals. ? agnd (sagnd) must be connected to the digital ground plane at the av dd (sav dd ) capacitor. ? the impedance of the ferrite bead should be much greater th an that of the capacitor at frequencies where noise is expected. table 12. overshoot and undershoot receiver ac overshoot (v) dc overshoot (v) dc undershoot (v) ac undershoot (v) t os 3.3v lvttl 3.9 3.6 0 -0.6 0.1*t cyc 1 2.5v (3.3v tolerant) 3.9 3.6 0 -0.6 0.1*t cyc 1 ddr 1.2*sov dd sov dd + 0.3 0 -0.6 0.1/memclkout pci 1.2*ov dd ov dd + 0.5 0 -0.2*ov dd 0.1/pciclk notes: 1. t cyc is the period of the bus clock. 1/perclk - ebc and nand flash interfaces. 1/emcrxclk - mii mode 1/emcrefclk - rmii mode 1/smiirefclk - smii mode 1/usb2clk - utmi 1/trcclk - instruction trace interface 1/iic0clk and 1/iic1clk - iic interfaces 1/spiclkout - spi l ? smt ferrite bead chip, murata blm21pg600sn1 c ? 0.1 f ceramic v dd av dd, sav dd agnd, sagnd gnd c l amcc proprietary 65 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 table 13. input capacitance parameter symbol maximum unit notes group 1 (2.5v sstl i/o) c in1 2.5 pf group 2 (3.3v lvttl i/o) c in2 2.1 pf group 3 (pci i/o) c in3 2.5 pf group 4 (receivers) c in4 0.9 pf group 5 (3.3v tolerant cmos i/o) c in5 2.4 pf group 6 (usb) c in6 4.5 pf table 14. typical dc power supply requirements frequency (mhz) +1.5v supply (v dd +av dd +sav dd ) +2.5v supply (sv dd ) +3.3v supply (ov dd ) total unit notes 333 1.00 1.15 0.04 2.19 w 1 400 1.09 1.15 0.04 2.28 w 1 533 1.28 1.15 0.04 2.47 w 1 667 1.93 1.15 0.04 3.12 w 1 notes: 1. typical power is based on nominal voltage of v dd = +1.5v, t c = max. specified in table 11 on page 62, while running linux and a test application that exerci ses each core with representative traffic. table 15. v dd supply power dissipation frequency (mhz) +1.4v +1.5v +1.6v unit notes 333 0.83 1.00 1.24 w 1 400 0.91 1.09 1.35 w 1 533 1.09 1.28 1.57 w 1 667 1.62 1.93 2.38 w 1 notes: 1. power is based on v dd specified in the table and t c = max. specified in table 11 on page 62, while running linux and a test application that exercises each core with representative traffic. 66 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor test conditions clock timing and switching characteristics ar e specified in accordance with operating conditions shown in the table ?recommended dc operating conditions.? ac specifications are characterized with v dd = 1.5v, t c = +85 c and a 50pf test load as shown in the figure to the right. table 16. dc power supply loads parameter symbol typical maximum unit notes v dd (1.5v) active operating current i dd 1250 1900 ma ov dd (3.3v) active operating current i odd 10 100 ma sv dd (2.5v) active operating current i sdd 460 600 ma av dd (1.5v) input current i add 3.2 5 ma 1 sav dd (1.5v) active operating current i sadd 6.05 10 ma 1 notes: 1. see ?absolute maximum ratings? on page 61 for filter recommendations. 2. the maximum current values listed above are not guaranteed to be the highest obtainable. thes e values are dependent on many factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, cas e temperature, and the power supply voltages. your s pecific application can produce significantly different results. v dd current and power are primarily dependent on the applications running and the use of inte rnal chip functions (dma, pci, ethernet, and so on). ov dd current and power are primarily dependent on the capacitive loading, fr equency, and utilization of the external buses. 3. typical current is estimated at 667mhz with v dd = +1.5v, ov dd = +3.3v, sv dd = +2.5v, and t c = +85c, while running linux and a test application that exercises each co re with representative traffic. 4. maximum current is estimated at 667mhz with v dd = +1.6v, ov dd = +3.6v, sv dd = +2.7v, and t c = +85c, and best-case process (which drives worst-case power), while running linux and a test application that exercises each core with representative traffi c. table 17. package thermal specifications thermal resistance values for the e-pbga package are as follows: parameter symbol package airflow ft/min (m/sec) unit notes 0 (0) 100 (0.51) 200 (1.02) junction-to-ambient thermal resistance without heat sink ja e-pbga 20.0 18.7 17.9 c/w te-pbga 15.6 13.6 12.8 c/w junction-to-ambient thermal resistance with heat sink ja e-pbga 15.3 11.9 10.5 c/w te-pbga 13.9 10.4 9.0 c/w resistance value junction-to-case thermal resistance jc e-pbga 8.3 c/w te-pbga 6.3 c/w junction-to-board thermal resistance jb e-pbga 14.3 c/w te-pbga 9.3 c/w output pin 50pf amcc proprietary 67 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 thermal management the following heat sinks were used in the above thermal analysis: alpha w35-15w (35mm x 35mm x15mm) alpha lpd35-15b (35mm x 35mm x15mm) the heat sinks are manufactured by: alpha novatech, inc. (www.alphanovatech.com) 473 sapena court, #12 santa clara, ca 95054 phone: 408-567-8082 notes: 1. case temperature, t c , is measured at top center of case su rface with device soldered to circuit board. 2. t a = t c - p ca , where t a is ambient temperature and p is power consumption. 3. t cmax = t jmax - p jc , where t jmax is maximum junction temperature (+125c) and p is power consumption. 4. the preceding equations assume that the chip is mount ed on a board with at least one signal and two power planes. 5. values in the table were achieved with a jede c standard board: 114.5mm x 101.6mm x 1.6mm, 4 layers. 6. values for an attached heat sink were achieved with a 35mm x 35mm x 15mm unit (see thermal management below), attached with a 0.1mm thickness of adhesive having a thermal conductivity of 1.3 w/mk. table 17. package thermal specifications thermal resistance values for the e-pbga package are as follows: parameter symbol package airflow ft/min (m/sec) unit notes 0 (0) 100 (0.51) 200 (1.02) 68 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor figure 5. timing waveform note: sysclk is 2.5v/3.3v tolerant receiver. slew ra te should be measured between 0.7v and 1.7v. table 18. clocking specifications symbol parameter min max units cpu clock f c frequency 333 667 sysclk input f c frequency 33.33 66.66 mhz t c period 15 30 ns t cs edge stability (cycle-to- cycle jitter) ? 0.15 ns t ch high time 40% of nominal period 60% of nominal period ns t cl low time 40% of nominal period 60% of nominal period ns note: input slew rate 1v/ns memclkout and plb clock f c frequency 100 133.33 mhz t c period 7.5 10 ns t ch high time 45% of nominal period 55% of nominal period ns pll vco f c frequency 600 1334 mhz t c period 0.7496 1.66 ns trcclk f c frequency cpu f c /4 cpu f c /4 mal clock f c frequency 45 83.33 mhz t c period 12 22.2 ns t cl t ch t c 1.7v (1.8v) 1.25v (1.5v) 0.7v (0.8v) amcc proprietary 69 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 spread spectrum clocking care must be taken when using a spread spectrum cloc k generator (sscg) with the ppc440gr. this controller uses a pll for clock generation inside the chip. the accura cy with which the pll follows the sscg is referred to as tracking skew. the pll bandwidth and phase angle determine how much tracking skew there is between the sscg and the pll for a given frequency deviation and modulation frequency. when using an sscg with the ppc440gr the following conditions must be met: ? the frequency deviation must not violate the minimum clock cycle time. therefore, when operating the ppc440gr with one or more internal clocks at their maximum supported frequency, the sscg can only lower the frequency. ? the maximum frequency de viation cannot exceed ? 3%, and the modulation frequency cannot exceed 40khz. in some cases, on-board ppc440gr peripherals impose more stringent requirements. ? use the peripheral bus clock for logic that is synchron ous to the peripheral bus since this clock tracks the modulation. ? use the ddr sdram memclkout sinc e it also tracks the modulation. notes: 1. the serial port baud rates are synchronous to the modulated clock. the serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. the 1.5% tolerance assumes that the connected device is runni ng at precise baud rates. 2. ethernet operation is unaffected. 3. iic operation is unaffected. important: it is up to the system designer to ensure th at any sscg used with the ppc440gr meets the above requirements and does not adversely affect other aspects of the system. 70 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor i/o specifications table 19. peripheral interface clock timings parameter min max units notes pciclk input frequency (asynchronous mode) ? 66.66 mhz pciclk period (asynchronous mode) 15 ? ns pciclk input high time 40% of nominal period 60% of nominal period ns pciclk input low time 40% of nominal period 60% of nominal period ns emcmdclk output frequency ? 2.5 mhz emcmdclk period 400 ? ns emcmdclk output high time 160 ? ns emcmdclk output low time 160 ? ns emctxclk input frequency mii 2.5 25 mhz emctxclk period mii 40 400 ns emctxclk input high time 35% of nominal period ? ns emctxclk input low time 35% of nominal period ? ns emcrxclk input frequency mii 2.5 25 mhz emcrxclk period mii 40 400 ns emcrefclk input frequency rmii (smii) 50 (125) 50 (125) mhz 2 emcrefclk period rmii (smii) 20 (8) 20 (8) ns emcrefclk input high time 35% of nomin al period 65% of nominal period ns emcrefclk input low time 35% of nominal period 65% of nominal period ns amcc proprietary 71 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 figure 6. input setup and hold waveform emcrxclk input high time 35% of nominal period ? ns emcrxclk input low time 35% of nominal period ? ns perclk (and opb clock) output frequency (for ext. master or sync. slaves) 33.33 66.66 mhz perclk period 15 30 ns perclk output high time 50% of nominal period 66% of nominal period ns perclk output low time 33% of nominal period 50% of nominal period ns uartserclk input frequency ? 1000 / (2t opb 1 +2ns) mhz 1 uartserclk period 2t opb +2 ?ns1 uartserclk input high time t opb +1 ?ns1 uartserclk input low time t opb +1 ?ns1 tmrclk1 input frequency ? 100 mhz 2 tmrclk1 period 10 ? ns tmrclk1 input high time 40% of nominal period 60% of nominal period ns tmrclk1 input low time 40% of nominal period 60% of nominal period ns notes: 1. t opb is the period in ns of the opb clock. t he internal opb clock runs at 1/2 the frequenc y of the plb clock. the maximum opb clock frequency is 66.66 mhz. 2. in rmii mode, 50mhz +/- 50ppm input emcrefclk is required. in smii mode, a 125 mhz +/- 100ppm input emcrefclk is required. table 19. peripheral interface clock timings (continued) parameter min max units notes clock t is t ih min min inputs valid 1.25v 72 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor figure 7. output delay and float timing waveform valid clock outputs valid t oh min t ov max t ov max t oh min t ov max t oh min float (high-z) high (drive) low (drive) 1.25v amcc proprietary 73 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 table 20. i/o specifications?pci, uart, iic, spi, et hernet, system and debug interfaces (sheet 1 of 2) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. 2. emcsync is a weak driver. redrive em csync when driving more than one load. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) pci interface pciad31:00 5 0 6 2 0.5 1.5 pciclk pcic3:0/be3:0 5 0 6 2 0.5 1.5 pciclk pcidevsel 5 0 6 2 0.5 1.5 pciclk pciframe 5 0 6 2 0.5 1.5 pciclk pcignt0:5 6 2 0.5 1.5 pciclk pciidsel 5 0 n/a n/a pciclk pciint 6 2 0.5 1.5 pciclk async pciirdy 5 0 6 2 0.5 1.5 pciclk pcipar 5 0 6 2 0.5 1.5 pciclk pciperr 5 0 6 2 0.5 1.5 pciclk pcireq0:5 5 0 n/a n/a pciclk pcireset n/a n/a pciclk pciserr 5 0 6 2 0.5 1.5 pciclk pcistop 5 0 6 2 0.5 1.5 pciclk pcitrdy 5 0 6 2 0.5 1.5 pciclk ethernet mii interface emccd 10 10 5.1 6.8 1, async emccrs 10 10 5.1 6.8 1, async emcdv 10 10 5.1 6.8 emcmdclk 5.1 6.8 1, async emcmdio 5.1 6.8 emcmdclk 1 emcrxclk 5.1 6.8 1, async emcrxd0:3 10 10 5.1 6.8 emcrxclk 1 emcrxerr 10 10 5.1 6.8 emcrxclk 1 emctxclk n/a n/a 1, async emctxd0:3 20 0 5.1 6.8 emctxclk 1 emctxen 20 0 5.1 6.8 emctxclk 1 emctxerr 20 0 5.1 6.8 emctxclk 1 rejectpkt 3 1 emcrxclk for mii, rmii, smii ethernet rmii interface emc0crsdv 4 2 emc0rxd0:1 4 2 5.1 6.8 emcrefclk 1 emc0rxerr 4 2 5.1 6.8 emcrefclk 1 emc0txd0:1 12.5 0 5.1 6.8 emcrefclk 1 emc1crsdv 4 2 emc1rxd0:1 4 2 5.1 6.8 emcrefclk 1 emc1rxerr 4 2 5.1 6.8 emcrefclk 1 emc1txd0:1 12.5 0 5.1 6.8 emcrefclk 1 74 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor ethernet smii interface emc0rxd 1.5 1 5.1 6.8 emcrefclk 1 emc0txd 3.5 0 5.1 6.8 emcrefclk 1 emc1rxd 1.5 1 5.1 6.8 emcrefclk 1 emc1txd 3.5 0 5.1 6.8 emcrefclk 1 emcsync 3.5 0 5.1 6.8 emcrefclk 1, 2 internal peripheral interface iic0sclk n/a 10.2 iic0sdata 5 0 n/a 10.2 iic0clk iic1sclk n/a 10.2 iic1sdata 5 0 n/a 10.2 iic1clk scpclkout n/a 10.2 scpdi 7 2 n/a 10.2 scpclkout scpdo 6 0 n/a 10.2 scpclkout uartn_rx na na async uartn_tx 10.3 7.1 async uartn_dcd na na async uartn_dsr na na async uartn_cts na na async uartn_dtr 10.3 7.1 async uartn_ri na na async uartn_rts 10.3 7.1 async interrupts interface irq0:9 na na async jtag interface tck na na async tdi na na async tdo 15.3 10.2 async tms na na async trst na na async system interface sysreset na na async halt na na async syserr 10.3 7.1 async gpio00:63 10.3 7.1 trace interface trcclk 10.3 7.1 trcbs0:2 10.3 7.1 trcclk trces0:4 10.3 7.1 trcclk trcts0:6 10.3 7.1 trcclk table 20. i/o specifications?pci, uart, iic, spi, et hernet, system and debug interfaces (sheet 2 of 2) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. 2. emcsync is a weak driver. redrive em csync when driving more than one load. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) amcc proprietary 75 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 table 21. i/o specifications?ebc, ebm i, dma and nand flash interfaces notes: 1. perclk rising edge at package pin with a 10pf load tr ails the internal plb clock by approximately 1.3ns. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) external slave peripheral interface dmaack0:1 10 1 5.1 6.8 perclk dmaack2:3 10 1 15.3 10.2 perclk dmareq0:3 11.7 0.5 na na perclk eot0:1/tc0:1 11.7 0.5 10 1 5.1 6.8 perclk eot2:3/tc2:3 11.7 0.5 10 1 15.3 10.2 perclk peraddr02:31 4 1 7.2 1.5 15.3 10.2 perclk perblast 4 1 6.5 1.5 15.3 10.2 perclk percs0:5 6.5 1.5 10.3 7.1 perclk perdata00:15 4 1 7.2 1.5 15.3 10.2 perclk peroe 6.5 1.5 15.3 10.2 perclk perready 6 1 15.3 10.2 perclk perr/w 4 1 6.5 1.5 15.3 10.2 perclk perwbe0:1 4 1 6.5 1.5 15.3 10.2 perclk external master peripheral interface busreq 6.5 1.5 7.1 9.6 perclk extack 6.5 1.5 7.1 9.6 perclk extreq 41 n/an/aperclk extreset 6.0 1.5 15.3 10.2 perclk holdack 6.5 1.5 7.1 9.6 perclk holdreq 4 1 na na perclk holdpri 4 1 na na perclk perclk 15.3 10.2 plb clk 1 pererr 6 1 10.3 7.1 perclk nand flash interface nfale 6.5 1.5 5.1 6.8 perclk nfce0:3 6.5 1.5 10.3 7.1 perclk nfcle 6.5 1.5 5.1 6.8 perclk nfrdybusy 4 1 na na perclk nfren 6.5 1.5 5.1 6.8 perclk nfwen 6.5 1.5 5.1 6.8 perclk 76 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor ddr sdram i/o specifications the ddr sdram controller times its oper ation with internal plb clock signals and generates memclkout0 from the plb clock. the plb clock is an internal signal that cannot be directly observed . however memclkout0 is the same frequency as the plb clock signal and is in phase with the plb clock signal. note: memclkout0 can be advanced with respect to th e plb clock by means of the sdram0_clktr programming register. in a typical system, users advance memclkout by 90 . this depends on the specific application and requires a thorough understanding of the memory system in general (refer to the ddr sdram controller chapter in the powerpc 440gr user?s manual ). in the following sections, the label me mclkout0(0) refers to memclkout0 when it has not been phase-shifted, and memclkout0(90) refers to memclkout0 when it has been phase-advanced 90 . advancing memclkout0 by 90 creates a 3/4 cycle setup time and 1/4 cycle hold time for the address and control signals in relation to memclkout0(90). the rising edge of memclkout0(90) a ligns with the first rising edge of the dqs signal. the following ddr data is generated by means of simulation and includes logic, driver, package rlc, and lengths. values are calculated over best case and worst case pr ocesses with speed, temperature, and voltage as follows: best case = fast process, -40 c, +1.6v worst case = slow process, +85 c, +1.4v note: in all the following ddr tabl es and timing diagrams, minimum values are measured under best case conditions and maximum values are measured under worst case conditions. the signals are terminated as indicated in the figure be low for the ddr timing data in the following sections. figure 8. ddr sdram simulati on signal termination model 10pf 10pf memclkout0 memclkout0 120 50 30pf addr/ctrl/data/dqs v tt = v dd /2 ppc440gr note: this diagram illustrates the model of the ddr sdram interface used when generating simulation timing data. it is not a recommended physical circuit design for this interface. an actual interface design will depend on many factors, including the type of memory used and the board layout. amcc proprietary 77 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 table 22. ddr sdram output driver specifications signal path output current (ma) i/o h (maximum) i/o l (minimum) write data memdata00:07 15.2 15.2 memdata08:15 15.2 15.2 memdata16:23 15.2 15.2 memdata24:31 15.2 15.2 ecc0:7 15.2 15.2 dm0:8 15.2 15.2 memclkout0 15.2 15.2 memaddr00:12 15.2 15.2 ba0:1 15.2 15.2 ras 15.2 15.2 cas 15.2 15.2 we 15.2 15.2 banksel0:3 15.2 15.2 clken0:3 15.2 15.2 dqs0:8 15.2 15.2 78 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor ddr sdram write operation the following diagram illustrates the relationship among the signals in volved with a ddr write operation. figure 9. ddr sdram write cycle timing note: the timing data in the following tables is based on simulation runs using einstimer. dqs memdata plb clk memclkout0 memclkout0(90) addr/cmd t sk t sa t ha t ds t ds t sd t hd t sd t hd t sa = setup time for address and command signals to memclkout0(90) t sk = delay from rising edge of memclkout0(0) to rising/falling edge of signal (skew) t ha = hold time for address and command signals from memclkout0(90) t ds = delay from rising/falling edge of clock to the rising/falling edge of dqs t sd = setup time for data signals (minimum time data is valid before rising/falling edge of dsq) t hd = hold time for data signals (minimum time data is valid after rising/falling edge of dsq) amcc proprietary 79 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 ddr sdram read operation the following examples of timing for ddr sdram read operations are based on the relationship between the table 23. i/o timing?ddr sdram t ds notes: 1. all of the dqs signals are referenced to memclkout0(0). 2. clock speed is 133mhz. 3. the t ds values in the table include 3/4 of a cycle at 133mhz (7.5ns x 0.75 = 5.625 ns). 4. to obtain adjusted values for lower clock frequencies, subtract 5.625 ns from the values in the table and add 3/4 of the cyc le time for the lower clock frequency (t ds - 5.625 + 0.75t cyc ). signal name t ds (ns) minimum maximum dqs0 5.76 5.86 dqs1 5.78 5.91 dqs2 5.82 5.90 dqs3 5.79 5.89 dqs8 5.75 5.88 table 24. i/o timing?ddr sdram t sk , t sa , and t ha notes: 1. clock speed is 133mhz. t sk is referenced to memclkout0(0). t sa and t ha are referenced to memclkout0(90). 2. to obtain adjusted t sa values for lower clock frequencies, use 3/4 of the cy cle time for the lower clock frequency and subtract t sk maximum (0.75t cyc - t sk max). 3. to obtain adjusted t ha values for lower clock frequencies, use 1/4 of the cycle time for the lower clock frequency and add t sk minimum (0.25t cyc + t sk min). signal name t sk (ns) t sa (ns) t ha (ns) minimummaximumminimum minimum memaddr00:12 0.11 0.32 5.31 1.99 ba0:1 0.07 0.31 5.32 1.95 banksel0:3 0.05 0.25 5.38 1.93 clken0:3 0.07 0.28 5.35 1.95 cas 0.05 0.31 5.32 1.93 ras 0.05 0.28 5.35 1.93 we 0.08 0.22 5.41 1.96 table 25. i/o timing?ddr sdram t sd and t hd notes: 1. t sd and t hd are measured under worst case conditions. 2. clock speed for the values in the table is 133mhz. 3. the time values in the table include 1/4 of a cycle at 166mhz (7.5ns x 0.25 = 1.875 ns). 4. to obtain adjusted t sd and t hd values for lower clock frequencies, subtract 1. 875 ns from the values in the table and add 1/4 of the cycle time for the lower clock frequency (e.g., t sd - 1.875 + 0.25t cyc ). signal names reference signal t sd (ns) t hd (ns) memdata00:07, dm0 dqs0 1.795 1.866 memdata08:15, dm1 dqs1 1.775 1.865 memdata16:23, dm2 dqs2 1.745 1.862 memdata24:31, dm3 dqs3 1.765 1.864 ecc0:7, dm8 dqs8 1.685 1.857 80 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor incoming data and the plb clock signal. since the pl b clock cannot be directly observed, the delay of memclkout(0) relative to the plb clock (t md ) is provided. the internal read clock signal, like memclkout0, is deriv ed from the plb clock and can be delayed relative to the plb clock by programming the rdct and rdcd fields in the sdram0_tr1 regi ster. the delay can be programmed from 0 to 1/2 cycle in steps using rdct. setting rdcd results in a 1/2 cycle delay plus the value set in rdct. the delay of read clock relative to the plb clock (t rd ) shown below assumes the programmable read clock delay is set to zero. figure 10. ddr sdram memclkout0 and read clock delay in operation, following the receipt of an address an d read command from the ppc440gr, the sdram generates data and the dqs signals coincident with memclkout0. the data is latched into the ppc440gr using a dqs signal that is delayed 1/4 of a cycle. in order to acco mmodate timing variations introduced by the system designs using this chip, the three-stage data path shown below is used to eliminate metastability an d allow data sampling to be adjusted for minimum latency. this adjustment requires programming the read clock delay and the selection of stage 1, stage 2, or stage 3 data for samp ling at read sample po int flipflop (rdsp). read clock plb clk memclkout0(0) t md t rd t md min = 600ps t md max = 1100ps t rd min = 300ps t rd max = 740ps amcc proprietary 81 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 figure 11. ddr sdra m read data path in the following examples, the data strobes (dqs) and the data are shown to be coincident. there is actually a slight skew as specified by the sdram specifications, an d there can be additional skew due to loading and signal routing. it is recommended that the signal length for all of the eight dqs signals be matched. table 26. i/o timing?ddr sdram t sin and t din notes: 1. t sin = delay from dqs at package pin to c on stage 1 ff. 2. t din = delay from data at package pin to d on stage 1 ff. 3. clock speed for the values in the table is 133mhz. 4. the time values for t sin include 1/4 of a cycle at 133mh z (7.5ns x 0.25 = 1.875 ns). signal name t sin (ns) minimum t sin (ns) maximum signal name t din (ns) minimum t din (ns) maximum dqs0 2.74 3.70 memdata00:07 0.86 1.87 dqs1 2.75 3.69 memdata08:15 0.87 1.86 dqs2 2.74 3.69 memdata16:23 0.89 1.86 dqs3 2.76 3.69 memdata24:31 0.88 1.85 dqs8 2.77 3.68 ecc0:7 0.89 1.83 stage 1 stage 2 stage 3 read sample point plb bus ff, ff ff ff data read select (sdram0_tr1[rdsl]) dqs 1/4 cycle delay plb clock programmed delay d c package pins mux read clock c c c d d d ff timing: t is = input setup time = 0.2ns t ih = input hold time = 0.1ns t p = propagation delay (d to q or c to q) = 0.4ns maximum xl ecc ff: flip-flop xl: transparent latch q q q q (sdram0_tr1[rdct]) flipflop (rdsp) 82 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor example 1: if the data-to-plb clock timing is as shown in the exampl e below, then the read clock is not delayed and the stage 1 data is sampled at (1) . except for small, low frequency memory sy stems with the memory located physically close to the ppc440gr, it is unlikely that stage 1 data can be sa mpled. when the data comes later, it is necessary to sample stage 2 or stage 3 data. (see examples 2 and 3). another way to get the desired data-to-plb timing to allow stage 1 sampling is to buffer me mclkout0 and skew it enough to guara ntee the timing. in this example, t t is controlled and set by the software. figure 12. ddr sdram read cycle timing?example 1 dqs at pin plb clock t sin t din = delay from data at package pin to d on stage 1 ff. t sin = delay from dqs at package pin to c on stage 1 ff. data at pin d0 d1 d2 d3 dqs stage 1 c d0 d1 d2 d3 t din d0 d2 data in stage 1 d d1 d3 data out stage 1 high low t p d0 d2 d1 d3 data in at rdsp high low with no ecc t t t p = propagation delay through ffs t t = propagation delay, stage 1 input to rdsp input w/o ecc d0 d2 d1 d3 data out rdsp high low (1) d2 d2 t p d0 d0 amcc proprietary 83 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 example 2: in this example read clock is delayed almost 1/2 c ycle. without ecc, stage 2 data can be sampled at (2) . if ecc is enabled, stage 3 data must be sample d (see example 3). in this example, t t and t te are controlled and set by the software. figure 13. ddr sdram read cycle timing?example 2 dqs at pin plb clock read clock delayed t sin data at pin d0 d1 d2 d3 dqs stage 1 c d0 d1 d2 d3 t din d0 d2 data in stage 1 d d1 d3 data out stage 1 high low t p d0 d2 d1 d3 data in at rdsp high low without ecc t t = propagation delay from stage 2 input to rdsp input w/o ecc d0 d2 d1 d3 data out stage 2 high low data out at rdsp high low (2) without ecc t p d0 d2 d1 d3 data in at rdsp high low with ecc d0 d2 d1 d3 t te = propagation delay from stage 2 input to rdsp input with ecc t t t te d0 d2 84 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor example 3: in this example, ecc is en abled. this requires that stage 3 data be sampled at (3) . if ecc is disabled, the system will still work, but there will be more latency befo re the data is sa mpled into rdsp. in this example, t t and t te are controlled and set by the software. figure 14. ddr sdram read cycle timing?example 3 dqs at pin plb clock read clock delayed t sin data at pin d0 d1 d2 d3 dqs stage 1 c d0 d1 d2 d3 t din d0 d2 data in stage 1 d d1 d3 data out stage 1 high low t p d0 d2 d1 d3 data out stage 3 high low with ecc t t = propagation delay from stage 2 input to rdsp input w/o ecc d0 d2 d1 d3 data out stage 2 high low data out rdsp high low (3) with ecc t p d0 d2 d1 d3 data in at rdsp high low with ecc d0 d2 d1 d3 t te = propagation delay from stage 2 input to rdsp input with ecc t te d0 d2 amcc proprietary 85 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 initialization the ppc440gr provides the option for setting initial paramete rs based on default values or by reading them from a slave prom attached to the iic0 bus (see ?serial eeprom? be low). some of the default values can be altered by strapping on external pins (see ?strapping? below). strapping while the sysreset input pin is low (system reset), the state of cert ain i/o pins is read to enable certain default initial conditions prior to ppc440gr start-up. the actual capture instan t is the nearest reference clock edge before the deassertion of reset. these pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired defau lt conditions. these pins are used fo r strap functions only during reset. following reset they are used for normal functions. the signal names assigned to the pins for normal operation are shown in parentheses following the pin number. note: to isolate the strapping pins, the extreset signal may be used as a buffer enable or multiplexer select. the following table lists the strapping pins al ong with their functions and strapping options: serial eeprom during reset, initial conditions other than those obtained from the strapping pins can be read from a rom device connected to the iic0 port. at the de-assertion of reset, if the boots trap controller is enabled, the ppc440gr sequentially reads 16b from the rom device on the iic0 port and sets the sdr0_sdstp0, sdr0_sdstp1, sdr0_sdstp2 and sdr0_sdstp3 registers accordingly. the initialization settings and their default values are covered in detail in the powerpc 440gr user?s manual . table 27. strapping pin assignments function option ball strapping r25 (uart0_dcd ) u26 (uart0_dsr ) v26 (uart0_cts ) serial device is disabled. ea ch of the six options (a? f) is a combination of boot source, boot-source width, and clock frequency specifications. refer to the iic bootstrap controller chapter in the ppc440gr embedded processor user?s manual for details. a 000 b 001 c 010 d 011 e 100 f 110 serial device is enabled. the option being selected is the iic0 slave address that will respond with strapping data. note: if reading of configuration data from the serial device fails, the ppc440gr defaults to configuration x. g (0xa8)101 h (0xa4)111 86 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor revision log date version contents of modification 01/12/2005 initial creation of document. 01/27/2005 restore second dma controller and make pvr and jtag id same as 440ep. 01/31/2005 update ddr sdram timing. 03/03/2005 update i/o definitions. misc. corrections 03/30/2005 remove 400mhz and 466mhz part numbers. 04/18/2005 remove reference to usb end points. 04/28/2005 update ddr sdram timing. 05/09/2005 update reserved signals and add description of tmrclk2. 05/18/2005 correct specs regarding the frequency range allowed for tmrclk2. 06/06/2005 1.08 change description of tmrclk2. 07/11/2005 1.09 add rohs compliance statement and change maximum nand flash to 256mb. 07/20/2005 misc. changes. 08/05/2005 change solder ball size specification. 09/21/2005 add power dissipation values for all supply voltages at the cpu speeds supported. 09/22/2005 1.10 transfer applicable data (input capacitance, thermal performance, etc.) from 400ep data sheet. 10/06/2005 1.11 misc. changes. 10/10/2005 1.12 add 400mhz cpu speed back into available pn list. 11/18/2005 1.13 add default configuration x when bootstrap iic read fails to table 27. add package nomenclature. correct memclkout duty cycle. correct description and move pererr signal from master to slave. change maximum vco frequency to 1334mhz. 02/16/2006 1.14 add revision level b (1.1) part numbers and pvr numbers. 05/24/2006 1.15 update power dissipati on and add additional temperature data. 07/19/2006 1.16 correct enable/disable sp ecifications for pci gnt/req signals. amcc proprietary 87 440gr ? ppc440gr embedded processor preliminary data sheet revision 1.19 ? may 07, 2008 12/03/2007 1.17 change analog voltage filter circuit inductor part number. change all multiplexed gpio signal defaults to the gpio signals. change ac12 default from irq5 to dmareq1. correct descriptions of leak test, rcvrinh, modectrl, refen, and drvrinh1:2 signals. added assembly requirements section on page 17, added unused i/os section on page 50, placed the analog filter diagram in its own section. added changes to the internal buses, changes to assembly requirements, moved diagram from under device characteristics to power sequencing and added more information, added information to ddr sdram read data path diagram, added information to test condition and i/o specifications diagrams. changed the technical support telephone and fax number. changed temperature rating for 333mhz and 400mhz parts on page 4 as per product change notification: 091207-01. added note for emcsync signal to i/o specification table. added timing references to i/o specification tables. corrected setup and hold timing for reje ctpk in i/o specification table. added definition for rdsp abbreviation to ddr sdram read data path figure. added notes 3 and 4 to recommended dc operating conditions table. added overshoot/undershoot specification. 03/18/2008 1.18 replaced 16750 compatible uart to 16550 replaced ns16750 with ns16550. 05/07/2008 1.19 deleted incorrect mdio timing data from table 20. date version contents of modification 88 amcc proprietary revision 1.19 ? may 07, 2008 preliminary data sheet 440gr ? ppc440gr embedded processor applied micro circuits corporation 215 moffett park drive, sunnyvale, ca 94089 phone: (408) 542-8600 ? fax: (408) 542-8601 http://www.amcc.com amcc reserves the right to make changes to its products, its data sheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially comp ly with the latest available data sheet. please consult amcc?s term and conditions of sale for its warranties and other terms, conditions and limitations. amcc may discontinue any semiconductor product or service wi thout notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the info rmation is current. amcc does not assume any lia - bility arising out of the application or use of any product or circuit described herein, neither does it convey any license und er its patent rights nor the rights of others. amcc reserves the ri ght to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed , intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. amcc is a registered trademark of appli ed micro circuits corporation. copyright ? 2006 applied micro circuits corporation. all rights reserved. |
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